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> I just think that Intel may be heading for a dead end--CISC
> chip technology is aging, and though we don't know what architecture the
> P6 will use yet, I'm guessing it will be yet another CISC chip.
Well the rumors from a reliable source (ie, Intel), are that the
P6 will be 4 - P5's (Pentium's) on a single substrate. It will still be a
32-bit chip, albeit a 4-way multi-processor.
Initially, Intel started developing the P7 to be a true 64-bit CISC chip.
Although Intel likes to call their architecture RISCified because it contains
pipelined instruction units, they are essentially classic CISC architectures.
The conserative (Intel) estimates calculated somewhere in the order of 16
million transistors for a 64-bit CISC chip.
Intel decided to punt this behemoth, and started romancing Hewlett Packard's
VLIW (very large instruction word) design team. VLIW is essentially RISC on
steroids. The idea behind VLIW is that you have many RISC instruction units in
parallel. The HP/Intel P6 supposedly has 18 such units. Like current RISC
architectures, this design decision places a large degree of the technical
difficulties on the compiler writers. The compiler for a VLIW machine must
sequence the RISC instructions so they do not violate data dependencies.
The VLIW P7 will of course _not_ use an X86 instruction set. Intel intends to
provide backward compatability through instruction set macros.
VLIW is a natural evolution of RISC, and a very exciting technology. I
sympathize with Intel's curse of backward compatability, and applaud this
rather dramatic decision.
| Robert George | Army Research Laboratory |
| robertg@assb01.arl.mil | AMSRL-SS-IC |
| Voice: (408) 656-3316 | 2800 Powder Mill Road |
| Fax: (408) 656-2814 | Adelphi, MD 20783-1197 |
A designer knows when he has achieved perfection not when there is
nothing left to add, but when there is nothing left to take away.
-- Antoine de Saint-Exupery