|TOSHIBA PCI to PC-Card16/CardBus Controller | |ToPIC100 | |Specification (2): | |Register | |Draft( Rev. 01.4 ) 1998-10-07 | Contents 6 Internal Registe.............................................5 6.1 Register ................................... ......................5 6.1.1PC-Card Configuration MAP ..5 6.1.2PC-Card 16 Register 6 6.1.3PC-Card 16 Register - continued 7 6.1.4CardBus Register 7 7 ToPIC100 Configuration Register 8 7.1 Vendor ID Register 8 7.2 Device ID Register 8 7.3 Command Register 9 7.4 Status Register 11 7.5 Revision ID Register 13 7.6 Class Code Register 13 7.7 Header Type Register 13 7.8 Base Address Register 13 7.9 Capability Pointer Register 15 7.10 Secondary Status Register 15 7.11 PCI Bus Number Register 17 7.12 Secondary Bus Number Register 17 7.13 Subordinate Bus Number Register 17 7.14 1st Memory window Base Register 18 7.15 1st Memory window Limit Register 18 7.16 2nd Memory window Base Register 19 7.17 2nd Memory window Limit Register 19 7.18 1st I/O window Base(Lower) Register 20 7.19 1st I/O window Base(Upper) Register 20 7.20 1st I/O window Limit(Lower) Register 20 7.21 1st I/O window Limit(Upper) Register 20 7.22 2nd I/O window Base(Lower) Register 21 7.23 2nd I/O window Base(Upper) Register 21 7.24 2nd I/O window Limit(Lower) Register 21 7.25 2ndI/O window Limit(Upper) Register 21 7.26 Interrupt Line Register 22 7.27 Interrupt Pin Register 22 7.28 Bridge Control Register 23 7.29 Subsystem Vendor ID Register 26 7.30 Subsystem Device ID Register 26 7.31 PC Card16 Legacy Mode Base Address Register 26 7.32 Capability ID Register 27 7.33 Next Item Ptr Register 27 7.34 Power Management Capabilities (PMC) Register 28 7.35 Power Management Control/Status (PMCSR) Register 29 7.36 PMCSR PCI to CardBus Bridge Support Extensions Register 30 7.37 Data Register 30 7.38 CardBus Socket Power Detect Control Register 31 7.39 ZV Control Register 32 7.40 Slot Control Register 33 7.41 Interrupt Control Register 34 7.42 Card Detect Control Register 35 7.43 CardBus Socket Register Control Register 36 7.44 Wake Up Control Register 38 7.45 Serial Interrupt Control Register 40 7.46 MISC1 Register 41 7.47 ZV Configuration Register 42 7.48 BUFFER CONTROL Register 43 7.49 Debug Register 44 7.50 Serial Power Control Register 46 7.51 IRQ Routing Register 47 7.52 Additional Control Register 49 7.53 Configuration Control Register 50 8 PC-Card16 Register 53 8.1 Identification and Revision Register 53 8.2 Interface Status Register 54 8.3 Power Control Register 55 8.4 Interrupt and General Control Register 58 8.5 Card Status Change Register 59 8.6 Card Status Change Interrupt Control Register 61 8.7 Window Enable Register 63 8.8 I/O Window Control Register 65 8.9 I/O Window 0 Start Low Address Register 67 8.10 I/O Window 0 Start High Address Register 67 8.11 I/O Window 0 Stop Low Address Register 67 8.12 I/O Window 0 Stop High Address Register 67 8.13 I/O Window 1 Start Low Address Register 68 8.14 I/O Window 1 Start High Address Register 68 8.15 I/O Window 1 Stop Low Address Register 68 8.16 I/O Window 1 Stop High Address Register 68 8.17 Memory Window 0 Start Low Address Register 69 8.18 Memory Window 0 Start High Address Register 69 8.19 Memory Window 0 Stop Low Address Register 70 8.20 Memory Window 0 Stop High Address Register 70 8.21 Memory Window 0 Offset Low Address Register 71 8.22 Memory Window 0 Offset High Address Register 71 8.23 Additional General Control Register 72 8.24 Memory Window 1 Start Low Address Register 74 8.25 Memory Window 1 Start High Address Register 74 8.26 Memory Window 1 Stop Low Address Register 75 8.27 Memory Window 1 Stop High Address Register 75 8.28 Memory Window 1 Offset Low Address Register 76 8.29 Memory Window 1 Offset High Address Register 76 8.30 Global Control Register 77 8.31 Memory Window 2 Start Low Address Register 78 8.32 Memory Window 2 Start High Address Register 78 8.33 Memory Window 2 Stop Low Address Register 79 8.34 Memory Window 2 Stop High Address Register 79 8.35 Memory Window 2 Offset Low Address Register 80 8.36 Memory Window 2 Offset High Address Register 80 8.37 Memory Window 3 Start Low Address Register 81 8.38 Memory Window 3 Start High Address Register 81 8.39 Memory Window 3 Stop Low Address Register 82 8.40 Memory Window 3 Stop High Address Register 82 8.41 Memory Window 3 Offset Low Address Register 83 8.42 Memory Window 3 Offset High Address Register 83 8.43 Memory Window 4 Start Low Address Register 84 8.44 Memory Window 4 Start High Address Register 84 8.45 Memory Window 4 Stop Low Address Register 85 8.46 Memory Window 4 Stop High Address Register 85 8.47 Memory Window 4 Offset Low Address Register 86 8.48 Memory Window 4 Offset High Address Register 86 8.49 ToPIC100 Card Timing Register 87 8.50 Audio/Video Switching Register 88 8.51 ToPIC100 Function Control Register 89 9 CardBus Register 90 9.1 Socket Event Register 90 9.2 Socket Mask Register 91 9.3 Socket Present State Register 92 9.4 Socket Force Register 95 9.5 Power Control Register 98 Internal Register 1 Register 1 PC-Card Configuration MAP |31 |23 |15 |07 |00 |Port | |Device ID(0617h) |Vendor ID(1179h) | 00h | |Status(0490h) |Command(0000h) | 04h | |Class Code(060700h) |Revision | 08h | | |ID(00h) | | | |Header | | | 0Ch | | |Type(82h) | | | | |Base Address | 10h | |Secondary Status | Latency |Capability | 14h | | |Timer |Pointer | | | |Subordinate Bus|Secondary Bus |PCI Bus Number | 18h | | | |Number | | | | |Number | | | | |1st Memory window Base | 1Ch | |1st Memory window Limit | 20h | |2nd Memory window Base | 24h | |2nd Memory window Limit | 28h | |1st I/O window Base (Upper) |1st I/O window Base (Lower) | 2Ch | |1st I/O window Limit (Upper) |1st I/O window Limit (Lower) | 30h | |2nd I/O window Base (Upper) |2nd I/O window Base (Lower) | 34h | |2nd I/O window Limit (Upper) |2nd I/O window Limit (Lower) | 38h | |Bridge Control |Interrupt Pin |Interrupt Line | 3Ch | |Subsystem Device ID(0000h) |Subsystem Vendor ID(0000h) | 40h | |PC Card16 Legacy Mode Base Address | 44h | | | | | |48h-7F| | | | | |h | |Power Management Capabilities |Next Item Ptr |Capability ID | 80h | |(PMC) | | | | |Data |PMCSR PCI to |Power Management Control/Status | 84h | | |CardBus Bridge |(PMCSR) | | | |Support | | | | | | | | 88h | |TOSHIBA RESERVED | 8Ch | | |90h | |CardBus Socket Power Detect Control | | | | | | |94h-9B| | | | | |h | | | | |ZV Control | 9Ch | |Card Detect | |Interrupt |Slot Control | A0h | |Control | |Control | | | |CardBus Socket Register Control | A4h | |Wake Up Control | A8h | |Internal PCI |ZV |MISC1 |Serial | ACh | |Retry |Configuration | |Interrupt | | | | | |Control | | |TOSHIBA RESERVED | | | | B0h | |TOSHIBA RESERVED | | | | B4h | |Debug |TOSHIBA RESERVED | | | B8h | | |Serial Power |TOSHIBA RESERVED | BCh | | |Control | | | |IRQ Routing | C0h | | | | |Additional | C4h | | | | |Control | | | | | | |C8-FBh| |Configuration Control | FCh | 6.1.2 PC-Card 16 Register (1)Base Address :Slot Control Register (A0h/Device ID:0617h) (2)Base Address :Base Address(10h/Device ID:0617h) |Offset(1|Offset(2|Register | |R/W |CLR | |) |) | | | | | |- |N/A |Port 3E Index |PP3EI7-0 |RW |P | |00h |800 |Identification and Revision |PPRVN7-0 |RW |P | |01h |801 |Interface Status |PPIFS7-0 |R |- | |02h |802 |Power Control |PPPCN7-0 |RW |P | |03h |803 |Interrupt and General Control |PPICN7-0 |RW |P | |04h |804 | |PPCSC7-0 |RW |P | |05h |805 |Card Status Change |PPCSI7-0 |RW |P | |06h |806 |Card Status Change Interrupt |PPWEN7-0 |RW |P | |07h |807 |Control |PPWCN7-0 |RW |P | |08h |808 |Window Enable |PPI0S7-0 |RW |P | |09h |809 |I/O Window Control |PPI0S15-8 |RW |P | |0Ah |80A | |PPI0E7-0 |RW |P | |0Bh |80B |I/O Window 0 Start Low Address |PPI0E15-8 |RW |P | |0Ch |80C | |PPI1S7-0 |RW |P | |0Dh |80D |I/O Window 0 Start High Address |PPI1S15-8 |RW |P | |0Eh |80E |I/O Window 0 Stop Low Address |PPI1E7-0 |RW |P | |0Fh |80F | |PPI1E15-8 |RW |P | |10h |810 |I/O Window 0 Stop High Address |PPM0S7-0 |RW |P | |11h |811 | |PPM0S15-8 |RW |P | |12h |812 |I/O Window 1 Start Low Address |PPM0E7-0 |RW |P | |13h |813 | |PPM0E15-8 |RW |P | |14h |814 |I/O Window 1 Start High Address |PPM0O7-0 |RW |P | |15h |815 | |PPM0O15-8 |RW |P | |16h |816 |I/O Window 1 Stop Low Address |PPACN7-0 |RW |P | |18h |818 | |PPM1S7-0 |RW |P | |19h |819 |I/O Window 1 Stop High Address |PPM1S15-8 |RW |P | |1Ah |81A | |PPM1E7-0 |RW |P | |1Bh |81B |Memory Window 0 Start Low Address |PPM1E15-8 |RW |P | |1Ch |81C | |PPM1O7-0 |RW |P | |1Dh |81D |Memory Window 0 Start High Address|PPM1O15-8 |RW |P | |1Eh |81E | |PPGCN7-0 |RW |P | |20h |820 |Memory Window 0 Stop Low Address |PPM2S7-0 |RW |P | |21h |821 |Memory Window 0 Stop High Address |PPM2S15-8 |RW |P | |22h |822 | |PPM2E7-0 |RW |P | |23h |823 |Memory Window 0 Offset Low Address|PPM2E15-8 |RW |P | |24h |824 | |PPM2O7-0 |RW |P | |25h |825 |Memory Window 0 Offset High |PPM2O15-8 |RW |P | |28h |828 |Address |PPM3S7-0 |RW |P | |29h |829 |Additional General Control |PPM3S15-8 |RW |P | |2Ah |82A | |PPM3E7-0 |RW |P | |2Bh |82B |Memory Window 1 Start Low Address |PPM3E15-8 |RW |P | |2Ch |82C |Memory Window 1 Start High Address|PPM3O7-0 |RW |P | |2Dh |82D | |PPM3O15-8 |RW |P | |30h |830 |Memory Window 1 Stop Low Address |PPM4S7-0 |RW |P | |31h |831 | |PPM4S15-8 |RW |P | |32h |832 |Memory Window 1 Stop High Address |PPM4E7-0 |RW |P | |33h |833 | |PPM4E15-8 |RW |P | | | |Memory Window 1 Offset Low Address| | | | | | | | | | | | | |Memory Window 1 Offset High | | | | | | |Address | | | | | | |Global Control | | | | | | |Memory Window 2 Start Low Address | | | | | | | | | | | | | |Memory Window 2 Start High Address| | | | | | | | | | | | | |Memory Window 2 Stop Low Address | | | | | | | | | | | | | |Memory Window 2 Stop High Address | | | | | | | | | | | | | |Memory Window 2 Offset Low Address| | | | | | | | | | | | | |Memory Window 2 Offset High | | | | | | |Address | | | | | | |Memory Window 3 Start Low Address | | | | | | |Memory Window 3 Start High Address| | | | | | | | | | | | | |Memory Window 3 Stop Low Address | | | | | | |Memory Window 3 Stop High Address | | | | | | |Memory Window 3 Offset Low Address| | | | | | | | | | | | | |Memory Window 3 Offset High | | | | | | |Address | | | | | | |Memory Window 4 Start Low Address | | | | | | |Memory Window 4 Start High Address| | | | | | | | | | | | | |Memory Window 4 Stop Low Address | | | | | | |Memory Window 4 Stop High Address | | | | 3 PC-Card 16 Register - continued. |Offset |Offset |Register | |R/W |CLR | |(1) |(2) | | | | | |34h |834 |Memory Window 4 Offset Low Address|PPM4O7-0 |RW |P | |35h |835 | |PPM4O15-8 |RW |P | |3Bh |83B |Memory Window 4 Offset High |PPCTM7-0 |RW |P | |3Ch |83C |Address |PPAVS7-0 |RW |P | |3Eh |83E |ToPIC100 Card Timing Register |PPTFN7-0 |RW |P | | | | | | | | | | |Audio/Video Switching Register | | | | | | |ToPIC100 Function Control Register| | | | NOTE:PC-Card 16 Register : Resume Clear can be executed by setting Power Control Register. 4 CardBus Register Base Address (10h/Device ID:0617h) |Offset | |NAME | |R/W|CLR| |000h | |Socket Event |PPSE31-0|R |P | |004h | |Socket Mask | |RW |P | |008h | |Socket Present State |PPSM31-0|R |P | |00Ch | |Socket Force | |W |P | |010h | |Power Control |PPSS31-0|RW |P | | | | | | | | | | | |PPSF31-0| | | | | | | | | | | | | |PPPC31-0| | | ToPIC100 Configuration Register 7.1 Vendor ID Register Vendor ID Register maintains vendor ID. Default value will be on after re-setting. This register is Configuration Control Register (Config. offset: FCh): Write is enabled when ID Write Enable bit is 1b. Configuration Control Register (Config. offset: FCh): The register is read only when ID Write Enable bit is 0b. |Config|NAME |RW |D16 |D0 |PCLR | |00h |PPVID |R | | |1179h | 7.2 Device ID Register Device ID Register maintains vendor ID. Default value will be on after re-setting. This register is Configuration Control Register (Config. offset : FCh) : Write is enabled when ID Write Enable bit is 1b. Configuration Control Register (Config. offset : FCh) : The register is read only when ID Write Enable bit is 0b. |Config|NAME |RW |D31 |D16 |PCLR | |02h |PPDID |R | | |0617h | 7.3 Command Register |Config|NAME |RW |D15 |D14 |D13 |D12 |D11 |D10 |D9 |D8 |PCLR | |04h |PPCMD |RW |- |- |- |- |- |- |MFBE |SRRE |0000h| | | | |D7 |D6 |D5 |D4 |D3 |D2 |D1 |D0 | | | | | |WCC |PERE |- |MWIE |SCE |BME |MAE |IOAE | | D9: Fast Back-to-Back Enable bit This field is fixed "0". Because a master can not do fast back-to-back transactions to different devices. D8: SERR# Enable bit This is Enable bit for ToPIC100 to output SERR# signal to internal PCI bus (Primary bus). * ToPIC100 has no SERR# bin, and this bit has a meaning of set condition for Status Register-Signaled System Error bit (Config.Reg.06H-D14) . Reset to 0b. 1b: When you get Parity Error in the address phase of access to ToPIC100 on internal PCI bus, ToPIC100 asserts SERR# onto the internal PCI bus. (It happens only when SERR# enable bit and Parity Error Response bit are active in both A and b slots .) ToPIC100 also asserts SERR# onto the internal PCI bus when System Error Signal (CSERR#) on CardBus is active, but not onto the external PCI bus. 0b: ToPIC100 runs ignoring Parity Error in the address phase of access to ToPIC100 on the internal PCI Bus. ToPIC100 does not assert SERR# onto the internal PCI bus when System Error Signal (CSERR#) on CardBus is active. D7: Wait cycle control bit This field is fixed "0". Because an address/data stepping is not supported. D6: Parity Error Response bit This is control bit that works to ToPIC100 when you get Parity Error in the access to ToPIC100 on the internal PCI bus (primary bus). Reset to 0b. 1b: SERR#,PERR# Enable 0b: Disable ToPIC100 works as follows when you get Parity Errors in the access to ToPIC100 on the internal PCI Bus (primary bus). Case 1 : Address phase - ToPIC100 asserts SERR# onto the internal PCI bus (primary bus) when both SERR# Enable bit (D8) and Parity Error Response bit (D6) for Config.Reg.04H are set in both A and B slots. It does not work unless eithr one is set, and can not assert SERR# on to the external PCI Bus. Case 2 : Data phase - ToPIC100 asserts PERR# onto the internal PCI bus (primary bus) when Parity Error Response bit (D6) is set in both A and B slots. It does not work unless either slot has Parity Error Response bit set. Note that ToPIC100 does not have PERR pin, so it doesn't assert PERR#. D4: Memory Write and invalidate Enable bit This field is fixed "0". Every memory write operation is carried out by the Memory Write Command. D3: Special Cycle bit This field is fixed "0". Because a response to Special Cycle operation is not supported. D2: Bus Master Enable bit Enable to act as a master on the PCI Bus and CardBus. 1: Possible to act as a master on the PCI Bus and CardBus. 0: Impossible to act as a master on the PCI Bus and CardBus. Responds to the access from PC card for CardBus by master-abort. D1: Memory Access Enable bit 1: Possible to respond to memory space accesses. 0: Impossible to respond to memory space acceses. D0: I/O access Enable bit 1: Possible to respond to I/O space accesses. 0: Impossible to respond to I/O space accesses. 7.4 Status Register Maintain status information of the internal PCI bus. Read and write enabled bit becomes 0b by writing 1b. |Config|NAME |RW |D15 |D14 |D13 |D12 |D11 |D10 |D9 |D8 |PCLR | |06h |PPST |R |DPER |SSER |RMAB |RTAB |STAB |DVT1 |DVT0 |DPDT |0490h| | | | |D7 |D6 |D5 |D4 |D3 |D2 |D1 |D0 | | | | | |FBBE |- |- |NCAP |- |- |- |- | | D15: Detected Parity Error bit This field is set to "1" if this controller detects a parity error when it acts as a master or a target on the PCI Bus. D14: Signaled System Error bit This field is set to "1" if this controller signal that it asserts SERR# on the PCI Bus. D13: Received Master Abort bit This field is set to "1" if this controller terminates its transaction with master-abort when it acts as a master on the PCI Bus. D12: Received Target Abort bit This field is set to "1" if this controller is terminated its transaction by target-abort when it acts as a master on the PCI Bus. D11: Signaled Target Abort bit This field is set to "1" if this controller terminates a transaction with target- abort when it acts as a master on the PCI Bus. D10-D9: DEVSEL# Timing 0 0: Fast 0 1: Medium 1 0: Slow 1 1: sub D8: Data Parity Detected bit This field is set to "1" by the following conditions. 1) This controller asserted PERR# itself or observed PERR# asserted. 2) PERR# asserted when this controller acts as a master on the PCI Bus. 3) When Parity Error Response of Command Register (Config: 04h) is set to "1". D7: Fast Back-to-Back Capable bit ("1" fixed) 1: Enable 0: Disable D4: New Capabilities It shows if NOVA can implement the list for extended capabilities such as PCI Power Management. 1b: shows New Capabilities (list for PCI Power Management) exist. (Implementation enabled.) 0b: shows New Capabilities (list for PCI Power Management) is not implemented. D15 - D11 and D8 are reset to "0" by writing "1". 7.5 Revision ID Register Revision ID Register maintains Revision ID for ToPIC100. Default value after reset. Configuration Control Register - ID Write Enable bit (Config. Reg.FCH- D0) =1b write enabled. = 0b read only. |Config|NAME |RW |D7 |D0 |PCLR | |08h |PPRID |RW | | |00h | 7.6 Class Code Register Class Code Register maintains Class Code for ToPIC100. ToPIC100 is PCI Bridge Device (06) which maps system resource (I/O, memory) to PC card, and works with CardBus card (07). The default value is 060700h. Default value after reset. Configuration Control Register-ID Write Enable bit (Config. Reg.FCH-D0) = 1b write enabled. = 0b read only |Config|NAME |RW |D31 |D8 |PCLR | |09h |PPCC |RW | | |060700h | 7.7 Latency Timer Register ToPIC100 does not support Latency Timer and 00h fixed. |Config|NAME |RW |D23 |D16 |PCLR | |0Dh |PPLT |R | | |00h | 7.8 Header Type Register ToPIC100 is multi-functional device and PCI-to-CardBus bridge device, bit 7 and bit1 are 1b. |Config|NAME |RW |D23 |D16 |PCLR | |0Eh |PPHT |R | | |82h | 7.9 Base Address Register |Config|NAME |RW |D31 | | |D12 |D11 |D1 |D0 |PCLR | |10h |PPBA |RW |BA31-12| | | |- | |- |0h | D31-D12: Base Address Sets up the base-address for mapping a Register-set of PC- Card16 and CardBus into the system resource. The Register-set of PC-Card16 and CardBus is mapped into 4K byte memory fields from this base address. The CardBus Register-set is mapped between 7FFh from 000h of the 4K Byte memory field. The PC-Card16 Register-set is mapped between FFFh from 800h of the 4K memory field. (The PC- Card16 Register-set is mapped at the head in the address which added the offset value in PC-Card16 Regster to 800h.) |Base Address | |Base | | |CardBus Register Set |Address+000h | | | | | | | |Base | | | |Address+7FFh | | | |Base | | |PC-Card16 Register Set |Address+800h | | | | | | | |Base | | | |Address+FFFh | 7.10 Capability Pointer Register |Config|NAME |RW |D7 |D6 |D5 |D4 |D3 |D2 |D1 |D0 |PCLR | |14h |CID |R |CPT7 |CPT6 |CPT5 |CPT4 |CPT3 |CPT2 |CPT1 |CPT0 |80h | D7-D0: Cap_Ptr Cap_Ptr provides Offset in the NOVA's PCI configuration field to the position of the first item (PCI Power Management registers) on the Capabilities Linked List. In NOVA, double word on the PCI header in 80h and 84h are PCI Power Management registers. 7.11 Secondary Status Register Secondary Status Register has similar functions to Status Register that is defined in the PCI Bus specification, however it shows the status for CardBus. Secondary Status Register is different from Status register in 14bit Received System Error bit, which is Signaled System Error bit in Status Register. |Config|NAME |RW |D15 |D14 |D13 |D12 |D11 |D10 |D9 |D8 |PCLR | |16h |PPCMD |RW |DPER |RSER |RMAB |RTAB |STAB |DVT1 |DVT0 |DPDT |0480h| | | | |D7 |D6 |D5 |D4 |D3 |D2 |D1 |D0 | | | | | |FBBE |- |- |- |- |- |- |- | | D15: Detected Parity Error bit This field is set to "1" if this controller detect a parity error when it acts as a master or a target on the CardBus. D14: Received System Error bit This field is set to "1" if this controller receive that SERR# is asserted on the CardBus. D13: Received Master Abort bit This field is set to "1" if this controller terminates its transaction with master-abort when it acts as a master on the CardBus. D12: Received Target Abort bit This fiels is set to "1" if this controller is terminated its transaction by target- abort when it acts as a master on the CardBus. D11: Signaled Target Abort bit This field is set to "1" if this controller terminates a transaction with target- abort when it acts as a target on the CardBus. D10-D9: DEVSEL# Timing 00b: Fast 01b: Medium 10b: Slow 11b: sub D8: Fast Back-to-Back Capable bit This field is set to "1" by the following conditions. 1) This controller asserted PERR# itself or observed PERR# asserted. 2) PERR# asserted whe this controller acts as a master on the PCI Bus. 3) When Parity Error Response of Bridge Control Register (config: 3Eh) is set to "1". D7: Fast Back-to-Back Capable bit ("1" fixed) 1: Enable 0: Disable D15 - D11 and D8 are reset to "0" by writing "1". 7.12 PCI Bus Number Register PCI Bus Number Register stores Bus Number of the internal PCI Bus (Primary Bus) connected to ToPIC100. Configuration SoftWare configures PCI Bus Number Register. |Config|NAME |RW |D7 |D6 |D5 |D4 |D3 |D2 |D1 |D0 |PCLR | |18h |PPPBN |RW |BNO7 |BNO6 |BNO5 |BNO4 |BNO3 |BNO2 |BNO1 |BNO0 |00h | D7-D0: PCI Bus Nmber This register holds the number of the PCI Bus. 7.13 Secondary Bus Number Register Secondary Bus Number Register stores Bus Number of CardBus connected to ToPIC100. Configuration SoftWare configures Secondary Bus Number Register. ToPIC100 converts Type 1 configuration cycle on the internal PCI Bus into Type 0 configuration cycle on CardBus when the bus number matches to Secondary Bus Number Register. |Config|NAME |RW |D7 |D6 |D5 |D4 |D3 |D2 |D1 |D0 |PCLR | |19h |PPSCN |RW |CNO7 |CNO6 |CNO5 |CNO4 |CNO3 |CNO2 |CNO1 |CNO0 |00h | D7-D0: CardBus Bus number This register holds the number of the CardBus attached to the socket. 7.14 Subordinate Bus Number Register The bus number of Type1 configuration cycle on the internal PCI Bus is larger than Secondary Bus Number Register. When the bus number is smaller than Subordinate Bus Number Register AND the davice number of Type1 configuration cycle is 0_0001b, ToPIC100 converts Type1 configuration cycle on to CardBus. |Config|NAME |RW |D7 |D6 |D5 |D4 |D3 |D2 |D1 |D0 |PCLR | |1Ah |PPSBN |RW |SNO7 |SNO6 |SNO5 |SNO4 |SNO3 |SNO2 |SNO1 |SNO0 |00h | D7-D0: Subordinate CardBus Bus Number This register holds the numebr of the CardBus at the lowest part of the hierarchy when the CardBus attached hierarchically. 7.15 1st Memory window Base Register 1st Memory window Base Register shows the start address that needs to have Memory Access on the internal PCI Bus execute on the 1st-Memory-window on CardBus. It gets expired when the superordinate 20 bit of 1st Memory window Limit Register(Config. offset : 20h) is all0b. (Address Decode does not execute.) |Config|NAME |RW |D31 | | | |D12 |D11 | |D0 |PCLR | |1Ch |PP1MB |RW |AD31 | | | |AD12 |- | | |00000h | The upper 20 bits define AD<31:12> on CardBus. The lower 12 bits are set to 0b fixed. The memory space is given on CardBus on a 4K bite boundary by this register and 1st Memory window Limit Register(Config. offset : 20h). D31-D12: 1st Memory Window Start Address This register holds a base address for forwarding a memory transaction on the PCI Bus to the CardBus. It defines AD31-12 on the CardBus. The lower 12 bits are all 000h. The memory space of the Card Bus is starting on a 4K boundary. 7.16 1st Memory window Limit Register 1st Memory window Limit Register shows the limit address that needs to have Memory Access on the internal PCI Bus execute on 1st-Memory- window on CardBus. ToPIC100 does not respond to Memory Access to CardBus for the 1st- Memory-window (Address Decode does not execute) when the superordinate 20 bit is all0b. |Config|NAME |RW |D31 | | | |D12 |D11 | |D0 |PCLR | |20h |PP1ML |RW |AD31 | | | |AD12 |- | | |00000h | The upper 20 bits define AD<31:12> on CardBus. The lower 12 bits are set to 1b fixed, but they are all set to 000h when a read access. The memory space is given on CardBus on a 4K bite boundary by this register and 1st Memory window Base Register (Config. offset : 1Ch). D31-D12: 1st Memory Window Limit Address This register holds a limit address for forwarding a memory transaction on the PCI Bus to the CardBus. It defines AD31-12 on the CardBus. The lower 12 bits are all fixed FFFh, but they are all set to 000h when a read access. If the AD31-12=00000h, any memory access is not accepted. 7.17 2nd Memory window Base Register 2nd Memory window Base Register shows the start address of the address range that needs to have Memory Access on the internal PCI Bus execute on 2nd Memory-window on CardBus. It gets expired when the superordinate 20 bit of ?2nd Memory window Limit Register(Config. offset : 28h) is all0b. (Address Decode does not execute.) |Config|NAME |RW |D31 | | | |D12 |D11 | |D0 |PCLR | |24h |PP2MB |RW |AD31 | | | |AD12 |- | | |00000h | The upper 20 bits define AD<31:12> on CardBus. The lower 12 bits are set to 0b fixed. The memory space is given on CardBus on a 4K bite boundary by this register and 2nd Memory window Limit Register(Config. offset : 28h). D31-D12: 2nd Memory Window Start Address This register holds a base address for forwarding a memory transaction on the PCI Bus to the CardBus. It defines AD31-12 on the CardBus. The lower 12 bits are all 000h. The memory space on the CardBus is starting on a 4K boundary. 7.18 2nd Memory window Limit Register 2nd Memory window Limit Register shows the limit address of the address range that needs to have Memory Access on the internal PCI Bus execute on 2nd Memory-window on CardBus. ToPIC100 does not respond to Memory Access to CardBus for the 2nd- Memory-window when the superordinate 20 bit is all0b. (Address Decode does not execute) |Config|NAME |RW |D31 | | | |D12 |D11 | |D0 |PCLR | |28h |PP2ML |RW |AD31 | | | |AD12 |- | | |00000h | The upper 20 bits define AD<31:12> on CardBus. The lower 12 bits are set to 1b fixed, but they are all set to 000h when a read access. The memory space is given on CardBus on a 4K bite boundary by this register and 2nd Memory window Base Register(Config. offset : 24h). D31-D12: 2nd Memory Window Limit Address This register holds a limit address for forwarding a memory transaction on the PCI Bus to the CardBus. It defines AD31-12 on the CardBus. The lower 12 bits are all FFFh, but they are all set to 000h when a read access. If the AD31-12=00000h, any memory access is not accepted. 7.19 1st I/O window Base(Lower) Register |Config|NAME |RW |D15 | | | | |D2 |D1 |D0 |PCLR | |2Ch |PP1IBL |RW |AD15 | | | | |AD2 |- |- |0000h| D15-D2: 1st I/O Window Start Address This register holds a lower 16 bits of a base address for forwarding a I/O transaction on the PCI Bus to the CardBus. It defines AD15-2 on the CardBus. The lower 2 bits of this register are all set to 00b. The I/O space on the Card Bus is starting on a 4K boundary. 7.20 1st I/O window Base(Upper) Register |Config|NAME |RW |D15 | | | | | | |D0 |PCLR | |2Eh |PP1IBU |R |AD31 | | | | | | |AD16 |0000h| D15-D0: 1st I/O Window Start Address ("0000h fixed") This register holds a upper 16 bits of a base address for forwarding a I/O transaction on the PCI Bus to the CardBus. This conrtoller supports the I/O space in 64K, and this register is fixed "0000h". It defines AD31-16 on the CardBus. 7.21 1st I/O window Limit(Lower) Register |Config|NAME |RW |D15 | | | | |D2 |D1 |D0 |PCLR | |30h |PP1ILL |RW |AD15 | | | | |AD2 |- |- |0000h| D15-D2: 1st I/O Window Stop Address This register holds a lower 16 bits of a limit address for fowarding a I/O transaction on the PCI Bus to the CardBus. It defines AD15-2 on the CardBus. The lower 2 bits of this register are set to 11b. It the AD15-2=0000h, any I/O access is not accepted. 7.22 1st I/O window Limit(Upper) Register |Config|NAME |RW |D15 | | | | | | |D0 |PCLR | |32h |PP1ILU |R |AD31 | | | | | | |AD16 |0000h| D15-D0: 1st I/O Window Stop Address ("0000h" fixed) This register holds a upper 16 bits of a limit address for forwarding a I/O transaction on the PCI Bus to the CardBus. This conrtoller supports the I/O space in 64K, and this register is fixed "0000h". It defines AD31-16 on the CardBus. 7.23 2nd I/O window Base(Lower) Register |Config|NAME |RW |D15 | | | | |D2 |D1 |D0 |PCLR | |34h |PP2IBL|RW |AD15 | | | | |AD2 |- |- |0000h | D15-D2: 2nd I/O Window Start Address This register holds a lower 16 bits of a base address for forwarding a I/O transaction on the PCI Bus to the CardBus. It defines AD15-2 on the CardBus. The lower 2 bits of this register are set to "00b". The I/O space on the CardBus is starting on a 4K boundary. 7.24 2nd I/O window Base(Upper) Register |Config|NAME |RW |D15 | | | | | | |D0 |PCLR | |36h |PP2IBU |R |AD31 | | | | | | |AD16 |0000h | D15-D0: 2nd I/O Window Start Address ("0000h" fixed) This register holds a upper 16 bits of a base address for forwarding a I/O transaction on the PCI Bus to the CardBus. This conrtoller supports the I/O space in 64K, and this register is fixed "0000h". It defines AD31-16 on the CardBus. 7.25 2nd I/O window Limit(Lower) Register |Config|NAME |RW |D15 | | | | |D2 |D1 |D0 |PCLR | |38h |PP2ILL|RW |AD15 | | | | |AD2 |- |- |0000h | D15-D2: 2nd I/O Window Stop Address This register holds a lower 16 bits of a limit address for forwarding a I/O transaction on the PCI Bus to the CardBus. It defines AD15-2 on the CardBus. The lower 2 bits of this register are set to "11b". If the AD15-2=0000h, any I/O access is not accepted. 7.26 2ndI/O window Limit(Upper) Register |Config|NAME |RW |D15 | | | | | | |D0 |PCLR | |3Ah |PP2ILU|R |AD31 | | | | | | |AD16 |0000h | D15-D0: 2nd I/O Window Stop Address ("0000h" fixed) This register holds a upper 16 bits of a limit address for forwarding a I/O transaction on the PCI Bus to the CardBus. This conrtoller supports the I/O space in 64K, and this register is fixed "0000h". It defines AD31-16 on the CardBus. 7.27 Interrupt Line Register |Config|NAME |RW |D7 |D6 |D5 |D4 |D3 |D2 |D1 |D0 |PCLR | |3Ch |PPITRL |RW |IL7 |IL6 |IL5 |IL4 |IL3 |IL2 |IL1 |IL0 |00h | D7-D0: Interrupt level bit The initialization program holds this bit. Device drivers and OS read the value on demand. 7.28 Interrupt Pin Register |Config|NAME |RW |D7 |D6 |D5 |D4 |D3 |D2 |D1 |D0 |PCLR | |3Dh |PPITRP |R |- |- |- |- |- |- |IPS1 |IPS0 |00h | D7-D2: Reserved 0b : fixed D1-D0: Interrupt Pin select bit These fields assign the data holded in the Interrupt Control Registe - Interrupt Pin Assign bit (Config. offset : A1h-D4,D5). 0 0b : Disable 0 1b : Interrupt assigned to INTA. 1 0b : Interrupt assigned to INTB. 11b : Reserved. 7.29 Bridge Control Register Bridge Control Register is expanded Command Register for PCI-CardBus Bridge specifications. |Config|NAME |RW |D15 |D14 |D13 |D12 |D11 |D10 |D9 |D8 |PCLR | |3Eh |PPBCN |RW |- |- |- |- |- |WBEN |M1PE |M0PE |0300h| | | | |D7 |D6 |D5 |D4 |D3 |D2 |D1 |D0 | | | | | |INTE |CBRS |MSAM |- |VGAE |ISAE |SERR |PERE | | D10 Write Buffer Enable bit 1b : Enable Write buffers are enabled. 0b : Disable D9: Memory 1 Prefetch Enable bit 1b : Enable Pre-fetch operation is carried out when a memory read transaction to the 2nd Memory Window space. 0b : Disable D8: Memory 0 Prefetch Enable bit 1b : Enable Pre-fetch operation is carried out when a memory read transaction to the 1st Memory Window space. 0b : Disable D7: IREQ-INT Enable bit 1b : Enable The interrupt signal from Card (BSYAZ/BSYBZ) is assigned to one of the serial interrupts signals (IRQ 3-15) in case of PC Card16/CardBus. The assignment is determined according to D3-0 of Interrupt and General Control Register (Offset : 03h). 0b : Disable The interrupt signal from Card (BSYAZ/BSYBZ) is assigned to INTAZ/INTB in case of PC-Card16/CardBus. The assignment is determined according to D5 - 4 of Interrupt Control Register (Offset : A1h). D6: CardBus Reset Enable 1b: Enable CRST# is enable to assert on the CardBus. 0b: Disable D5: Master Abort Mode bit This field control to signal a target abort during a master abort asserted. 1b: Possible t signal a target abort 0b: Impossible to signal a target abort. D3: VGA Enable bit 1b : Enable Possible to forward a transaction of VGA on the PCI Bus to the CardBus through the I/O spcae (3Boh - 3BBh, 3Coh - 3DFh) and the memory space (A0000h - BFFFFh). But a transaction to the PCI Bus from the CardBus is inhibited by a master abort. Configuration Register (in which I/O space and memory space and ISA enable are set up) is ineffective at this condition. 0b : Disable D2: ISA Enable bit 1b : Enable In the access to the CardBus from the PCI Bus, the transaction is forwarded to the lower 256 bytes of I/O space of the 1K-byte unit defined by the I/O window BaseXX register - the I/O window LimitXX register of a Configuratoin. In the access to the PCI Bus from the CardBus, the transaction is forwarded to the upper 768 bytes of I/O space of the 1K-byte unit defined by the I/O window BaseXX register - the I/O window LimitXX register of a Configuration. 0b : Disable The transaction is forwarded to the I/O space defined by the I/O window BaseXX Register - the I/O window LimitXX Register. D1: SERR# Enable bit 0b : Disable 1b : Enable SERR# signaled on the CardBus is related to D14 of status Register (Config : 06h), only when the D8 of Command Register (Config : 04h) is set to "1". D0: Parity Error Response Enable bit 0b : Disable 1b : Enable Possible to signal and detect an address/data parity error signaled on the CardBus. 7.30 Subsystem Vendor ID Register Configuration Control Register(Config. offset : FCh) : ID Write Enable bit 1b : Write enable 0b : Write disable - read only. |Config|NAME |RW |D15 |D14 |D13 |D12 |D11 |D10 |D9 |D8 |PCLR | |40h |PPSVID |RW |SV15 |SV14 |SV13 |SV12 |SV11 |SV10 |SV9 |SV8 |1179h| | | | |D7 |D6 |D5 |D4 |D3 |D2 |D1 |D0 | | | | | |SV7 |SV6 |SV5 |SV4 |SV3 |SV2 |SV1 |SV0 | | D15-D0: Subsystem Vendor ID bit 10 Subsystem Device ID Register Configuration Control Register(Config. offset : FCh) : ID Write Enable bit 1b : Write enable 0b : Write disable - read only. |Config|NAME |RW |D15 |D14 |D13 |D12 |D11 |D10 |D9 |D8 |PCLR | |42h |PPSDID |RW |SD15 |SD14 |SD13 |SD12 |SD11 |SD10 |SD9 |SD8 |0001h | | | | |D7 |D6 |D5 |D4 |D3 |D2 |D1 |D0 | | | | | |SD7 |SD6 |SD5 |SD4 |SD3 |SD2 |SD1 |SD0 | | D15-D0: System Device ID bit 11 PC Card16 Legacy Mode Base Address Register |Confi|NAME |RW |D31 | | |D16 |D15 |D1 |D0 |PCLR | |g | | | | | | | | | | | |44h |PPLMB |RW |- | | | |LMB15-1| |1 |01h | D15-D1: PC Card16 Bit IF Legacy Mode Base Address Bit This register holds a base address with Legacy Mode when Card Detect control Register (Config : A3h) is set to "0". Supports a Legacy Mode operation with non-zero address. D0: Reserved. 1b : fixed. 12 Capability ID Register |Confi|NAME |RW |D7 |D6 |D5 |D4 |D3 |D2 |D1 |D0 |PCLR | |g | | | | | | | | | | | | |80h |NVCID |R |CID7 |CID6 |CID5 |CID4 |CID3 |CID2 |CID1 |CID0 |01h | D7-D0: Cap_ID 01h : Shows the Items are PCI Power Management registers. 13 Next Item Ptr Register |Confi|NAME |RW |D7 |D6 |D5 |D4 |D3 |D2 |D1 |D0 |PCLR | |g | | | | | | | | | | | | |81h |NVNIPTR |R |NIP7 |NIP6 |NIP5 |NIP4 |NIP3 |NIP2 |NIP1 |NIP0 |00h | D7-D0: Next_Item_Ptr Assign Offset in PCI configuration space to Next Item. Set to 00h. 14 Power Management Capabilities (PMC) Register |Config|NAME |RW |D15 |D14 |D13 |D12 |D11 |D10 |D9 |D8 |PCLR | |82h |NVPMC |R |PME4 |PME3 |PME2 |PME1 |PME0 |D2SP |D1SP |- |FE11h | | | | |D7 |D6 |D5 |D4 |D3 |D2 |D1 |D0 | | | | | |- |- |DSI |VAPS |PMEC |VER2 |VER1 |VER0 | | D15-11: PME_Support 0b : PME# is not asserted at corresponded power state. D15 - 0b : Vaux is not supported. D15: 1XXXXb: PME# is asserted from D3cold. Set to 1b fixed. D14: X1XXXb: PME# is asserted from D3hot. Set to 1b fixed. D13: XX1XXb: PME# is asserted from D2. Set to 1b fixed. D12: XXX1Xb: PME# is asserted from D1. Set to 1b fixed. D11: XXXX1b: PME# is asserted from D0. Set to 1b fixed. D10: D2 Support Set to "1" fixed. 1b: Power Management State of D2 is supported. D9: D1 Support Set to "1" fixed. 1b: Power Management State of D1 is supported. D8-D6: Reserved Set to "000b" fixed. D5: DSI(Device Specific Initialization) Set to "0" fixed. D4: Auxiliary Power Source(VAUX) This field is effective only when D15 is 1b. Set to "1" fixed. 1b: To support PME# in D3cold, auxiliary power supplied via proprietary transmission path is needed. 0b: This controller itself supplies auxiliary power. D3: PME Clock Set to "0" fixed. 1b: PME# operation is affected by with or without PCI clock. 0b: PCI clock is not needed to generate PME#. D2-0: Version Set to "001b" fixed. 001b: This controller is 'The Revision 1.0 of the PCI Power Management Interface Specification' compliant. 15 Power Management Control/Status (PMCSR) Register |Config|NAME |RW |D15 |D14 |D13 |D12 |D11 |D10 |D9 |D8 |PCLR | |84h |NVPMCS |RW |PMES |DSC1 |DSC0 |DSL3 |DSL2 |DSL1 |DSL0 |PMEE |0000h| | | |/R |D7 |D6 |D5 |D4 |D3 |D2 |D1 |D0 | | | | | |- |- |- |- |- |- |PST1 |PST0 | | D15: PME status (Read only) 1b: This field is set to "1" when this controller assert PME#. It is independent from the status of PME_En(D8). Invalid when writing 0. D14-13: Data scale(Read only) 00b: Unknown 01b: 0.1x [W] 10b: 0.01x [W] 11b: 0.001x [W] D12-9: Data select 0000b: Electric power consumption for D0. 0001b: Electric power consumption for D1. 0010b: Electric power consumption for D2. 0011b: Electric power consumption for D3. 0100b: Heat loss for D0. 0101b: Heat loss for D1. 0110b: Heat loss for D2. 0111b: Heat loss for D3. 1000b: Electric power consumption for the common logic. D8: PME_En This fieled has to be cleared explicitly by OS when it is loaded. 1b: Enable. This controller asserts PME#. 0b: Disable. This controller is not able to assert PME#. D7-D2: Reserved (Read only) Set to "000000b" fixed. D1-0: PowerState This field determines current power state of this controller and holds new power state. However, when writing given power state which the transition at each power stae is not permitted, write operation ends normally, but the transition of the power state does not take place with the data disregarded. 00b: D0 01b: D1 10b: D2 11b: D3hot 16 PMCSR PCI to CardBus Bridge Support Extensions Register |Config|NAME |RW |D7 |D6 |D5 |D4 |D3 |D2 |D1 |D0 |PCLR | |86h |NVPPCBS |R |BPCC |B2B3 |- |- |- |- |- |- |80h | D7: Bus Power/Clock Control Enable (Read only) Set to "1" fixed. 1b : Bus Power/Clock Control mechanism is valid. 0b : Bus Power/Clock Control mechanism is invalid. In this case, System Software is not able to use PowerState bit (D1-D0) of PMCSR Register(Config. offset : 84) with the purpose of controlling power or clock. D6: B2_B3#(B2/B3 support for D3hot) (Read only) This field defines behevior resulted directly from this controller being programmed by D3hot. It is valid only when when D7 is "1". Set to "0" fixed. 1b : NOVA stops the clock to Secondary Bus when D3hot. (B2) 0b : NOVA stops the clock to Secondary Bus when D3hot , and it becomes defeasible for the power to Secondary Bus. (B3) D5-D0: Reserved (Read only) Set to "000000b" fixed. 17 Data Register |Config|NAME |RW |D7 |D6 |D5 |D4 |D3 |D2 |D1 |D0 |PCLR | |87h |NVDATA |R |- |- |- |- |- |- |- |- |00h | D7-D0: Reserved (Read only) Set to "00h" fixed. 7.38 CardBus Socket Power Detect Control Register This field holds the interval after the output of control signal for the card electric power when inserting the card. It starts identifying the card after the card electric power is stabilized. |Config|NAME |RW |D31 | | | | | | |D16 |PCLR | |90h |PPCSPDC |RW | | | | | | | | |0000h | | | |/R |D15 | | |D4 |D3 |D2 |D1 |D0 | | | | | |- |- |- |- |- |-PST2 |PST1 |PST0 | | D31-3: Reserved (Read only) Set to "00000000h" fixed. D2-0: Power Detect Timing bit This field controls wait timings of power supply. 000b: 2 ms wait 001b: 4 ms wait. 010b: 8 ms wait. 110b: 16 x PCICLK 111b: 4 x PCICLK others: Reserved 18 ZV Control Register |Config|NAME |RW |D7 |D6 |D5 |D4 |D3 |D2 |D1 |D0 |PCLR | |9Ch |PPZVC |RW |- |- |- |- |- |- |- |ZVCN |00h | D0: ZV Control bit 1b : ZV Enable AUDIO/VIDEO ZV port function is enabled. 0b : ZV Disable Possible to read a status of ZV port when D1 of MISC2 Register (Config : AEh) is set to "1". This bit is set to "1" if ZV port is used. It changes when D1 or D0 of Audio/Video switching Register (Offset : 3Ch) is changed, since they are related to each other. This is Audio/Video in common, it is set to "1" when either one of Card16 Reg.3Ch D1 or D0 is "1". 19 Slot Control Register Each slot has many control/status register sets. This register controls enable/disable in each slot and allocation of I/O port, etc. Note : Some registers have been added or changed based on Intel82092 (PPEC) in this controller. This register is PC-Card 16 PCMCIA Slot Control Register compatible. |Config|NAME |RW |D7 |D6 |D5 |D4 |D3 |D2 |D1 |D0 |PCLR | |A0h |PPSLT |RW |ESLT |EREG |EHDN |IDWP |PAD1 |PAD0 |OFS1 |OFS0 |00h | D7: SLOTON bit 1b : Enable CardBus slot function is enabled. 0b : Disable No response to the access for PC-Card16 register and CardBus register. D6: SLOTEN bit 1b : Enable The access to the register-set of PC-Card16 and CardBus is enabled. 0b : Disable D5: ID_LOCK bit This bit controls write access to the following registers. Card16 Reg. 3Bh : ToPIC100 Card Timing Register 3Eh : ToPIC100 Function Control Register 3Fh : Toshiba Hidden Register 1b : LOCK (Disable) The write access to Toshiba hidden Register (Offset : 3Fh) is enabled. 0b : UNLOCK (Enable) D4: ID_WP bit 1b : Write Protect The write access to ID & Revision Register (Offset : 00h) is enabled. 0b : Write Enable D3-D2: Slot Port Select bit This bit is valid when PC-Card16/32 mode Select bit in Card Detect Control Register (Config. offset : A3h) is "0". 00b : Index port 3E0h / Data port 3E1h 01b : Index port 3E2h / Data port 3E3h 10b : Index port 3E4h / Data port 3E5h 11b : Index port 3E6h / Data port 3E7h D1-D0: Offset Select bit This bit is valid when PC-Card16/32 mode Select bit in Card Detect Control Register (Config. offset : A3h) is "0". 00b : 00h - 3Fh 01b : 40h - 7Fh 10b : 80h - BFh 11b : C0h - FFh 20 Interrupt Control Register |Config|NAME |RW |D7 |D6 |D5 |D4 |D3 |D2 |D1 |D0 |PCLR | |A1h |PPIRC |RW |- |- |IPA1 |IPA0 |- |STIQ |IRPL |IRLN |00h | D5-D4: Interrupt Pin Assign bit These fields assign an interrupt to an external output signal . 00b : Disable 01b : Assign an interrupt to INTA 10b : Assign an interrupt to INTB 11b : Reserved D2: STSIRQNP bit This field set up an output mode of a status change interrupt. 1b : Pulse mode 0b : Through mode D1: IRQNP bit This field set up an output mode of an IRQ interrupt. 1b : Pulse mode 0b : Through mode D0: IRQ/INT select bit 0b: IRQ selected The status change interrupt (BVDAZ / BVDBZ) from Card is assigned to INTAZ / INTBZ in case of PC-Card 16. The assignment is determined according to D3 - 0 of Interrupt & General Control Register (Offset : 03h) 1b: INTA Selected The status change interrupt (BVDAZ/BVDBZ) from Card is assigned to INTAZ/INTBZ is case of PC- Card16. The assignment is determined according to D5 - 4 of Interrupt Control Register (Config : A1h) 21 Card Detect Control Register |Config|NAME |RW |D7 |D6 |D5 |D4 |D3 |D2 |D1 |D0 |PCLR | |A3h |PPCDT |RW |PCMD |- |- |- |- |VSS1 |VSS0 |DMSL |00h | D7: PC-Card16/32 mode Select bit 1b : PC-Card16 / CardBus mode 0b : PC-Card16 mode (Default) D2-D1: Voltage Sense Pin enable bit The external output signal VS2AZ / VS2BZ and VS1AZ / VS1BZ are enabled when a Card is detected by software (D0 of this register is set to "1".) 11b : VS2=Hi-Z, VS1 = Hi-Z (Default) 10b : VS2=Hi-Z, VS1 = LOW 01b : VS2=LOW, VS1 = Hi-Z 00b : VS2=LOW, VS1 = LOW D0: Detect Method Select bit This bit determines software / hardware to detect a card. 1b : A card is detected by software. 0b : A card is detected by hardware. (Default) 22 CardBus Socket Register Control Register |Config|NAME |RW |D31 |D30 |D29 |D28 |D27 |D26 |D25 |D24 |PCLR | |A4h |PPSRC |RW |RRE |CRRE |CKRN |CTST |IOPU|CRSE |SSPO |SSSO |0Ch | | | | |D23 | | |D16 |D15 D11 |D10 |D8 |PCLR | | | | |- | | |CBRE |CDD4-0 |- | |0000h| | | | |D7 | | | |D3 |D2 |D1 |D0 |PCLR | | | | |- | | | | |DRI |CAOF |CAIE |00h | D31: Resume Reset Enable bit 1b: Enable The CardBus Register-set are reset when resumed. 0b: Disable The CardBus Register-set are kept when resumed. D30: CardBus Card Removal Reset Enable bit 1b: Enable The CardBus Register-set are reset when CardBus is removed. 0b: Disable D29: CLKRUNEN bit 1b: Enable The CLKRUN function of CardBus is enabled. It has priority over Stop Clock bit (CB Reg.010h-D7) of Power Control Register. 0b: Disable D28: H256PCTE bit 1b: Test mode The 256PCICLK counter is used as 16PCICLK counter. 0b: Normal mode D27: IOPLUP bit 1b: The IO cell in the CardBus side are pulled up. 0b: Normal mode. (IO cell are not pulled up) D26: CardBus Reset Control bit 0b: Normal compatible mode (0 x PCICLK) 1b: 256 x PCICLK mode D25: SUSPEND Socket Power Off bit 1b: Power to the socket is turned off in case of suspend mode. 0b: Power to the socket is supplied in case of suspend mode. D24: SUSPEND Socket Signal Off bit 1b: Signal to the socket is set to "Hi-Z" in case of suspend. 0b:Signal to the socket is output in case of suspend. D16: CardBus Register Write Enable Mode bit 0b: Invalidate bite enable 1b: Validate bite enable. D15-D11: CardBus Device Number bit This field holds the CardBus Device Number. D2: RIOUTDIS bit Disable bit to RIOUT signal 1b: Disable 0b: Enable D1: CAUDIO Signal Off bit 1b: CAUDIO signal input is invalid. (No input) 0b: Input CAUDIO signal. D0: CAUDIO Invert Enable bit 1b: Enable CAUDIO signal input is inverted. 0b: Disable |PC Card Type | CAOF CAIE | AUDIO | |CardBus | 0 0 | CAUDIO | | |0 1 |~CAUDIO | |PC-Card16 | 0 0 |0 | | |0 1 |1 | |X | 1 0 |0 | | |1 1 |1 | 7.44 Wake Up Control Register |Config|NAME |RW |D31 |D14 |D13 |D12 |D11 |D10 |D9 |D8 |PCLR | |A8h |P PWUC|RW |- |RPOS |EC2W |EC1W |EB3W |EB2W |EB1W |EB0W |00h | | | | |D7 |D6 |D5 |D4 |D3 |D2 |D1 |D0 |PCLR | | | | |ESRW |EICW |EITW |ECSW |ESPS |ECLK |ECHG |SCHG |00h | D31-D15: Reserved (RW possible) D14: RI_OUT/PME# Pin Output Select 1b : Output RI_OUT from RI_OUT/PME# Pin. 0b : Output PME# from RI_OUT/PME# Pin. D13: CCD2# Pin WakeUp Enable 1b : Enable Wake-Up Event by CCD2# Pin is enabled. 0b : Disable D12: CCD1# Pin WakeUp Enable 1b : Enable Wake-Up Event by CCD1# Pin is enabled. 0b : Disable. D11: Socket Event Register PowerCycle bit WakeUp Enable 1b : Enable Wake-Up by Power Cycle bit of CB Register Socket Event Register is enabled. 0b : Disable. D10: Socket Event Register CCD2# bit WakeUp Enable 1b : Enable Wake-Up by CCD2# bit of CB Register Socket Event Register is enabled. 0b : Disable D9: Socket Event Register CCD1# bit WakeUp Enable 1b : Enable Wake-Up by CCD1# bit of CB Register Socket Event Register is enabled. 0b : Disable. D8: Socket Event Register CSTSCHG bit WakeUp Enable 1b : Enable Wake-Up by CSTSCHG bit of CB Register Socket Event Register is enabled. 0b : Disable D7: R2 STSCHG# Pin WakeUp Enable 1b : Enable Wake-Up by R2 STSCHG# Pin is enabled. 0b : Disable D6: R2 IREQ# Pin WakeUp Enable 1b : Enable Wake-Up by R2 IREQ# Pin is enabled. 0b : Disable D5: CB CINT# Pin WakeUp Enable 1b : Enable Wake-Up by CB CINT# Pin is enabled. 0b : Disabled D4: CB CSTSCHG Pin WakeUp Enable 1b : Enabled Wake-Up by CB CSTSCHG Pin is enabled. 0b : Disable D3: Socket Present Status Register Clear Enable 1b : Enable Socket Present Status Register is cleared by Card removal in case of Suspend mode. 0b : Disable D2: CLK32 Socket Event Register Enable 1b : Enable. Socket Event Register with CLK32 is used. D7 - D4 is enabled. 0b : Disable. D1: STSCHG Output Enable This bit is related to D8 (PEM_EN) of Power Management Control/Status (PMCSR) Register (Config. offset : 84h). Writing to D8 of Power Management Control/Status (PMCSR) Register reflects this bit. This controller has no usual STSCHG pin. RI_OUT/PME# Pin outputs STSCHG when D14 of this register is "0". 1b : Enable Internal output signal PCSTCG is enabled. External output signal STSCHGZ is enabled (set to "L") when D4 of Enable Register (I/O : 00EFh, index : 6Ch) is "1". 0b : Disable D0: STSCHG Status This field indicates condition of external output signal STSCHG. It is reset to "0" when written "1". This bit is related to Power Management Control/Status (PMCSR) Register (Config. offset : 84h)-D15(PME status). This bit is cleared when written "1" in the Register. 7.45 Serial Interrupt Control Register This register exists only one in this controller that controls Serial Interrupt and changes serial mode. |Config|NAME |RW |D7 |D6 |D5 |D4 |D3 |D2 |D1 |D0 |PCLR | |ACh |PPSIC |RW |VSST |CMS |VSIS |VSOS |VSSM |VSIM|SICM|00h | D7: VESA Serial Interrupt Status Bit (Read only) (R_STATE) 0b: Continuous Mode 1b: Quiet Mode D6: Continuous Mode Select Bit (R_CMODE) 0b: Carry breaking edge of the interrupt . 1b: Carry interrupt level in the Continuous Mode. D5-4: VESA Serial Interrupt Input Mode Select Bit (R_INFF) 00b: Fetch serial interrupt signal when PCICLK. is rising. 01b: Fetch serial interrupt signal when PCICLK is breaking. 10b: Fetch serial interrupt signal 5ns after PCICLK rose. D3: VESA Serial Interrupt Output Mode Select Bit (R_OUTFF) 0b: Output in sync with PCICLK rising. 1b: PCICLK in sync with PCICLK breaking. D2: VESA Serial Interrupt SMI Mapping Bit 0b:Direct output mode. 1b: Interrupt signal is output from Serial interrupt signal. D1: VESA Serial Interrupt INT Mapping Bit 0b: Direct output mode. 1b: Interrupt signal is output from Serial interrupt signal. D0: Serial Interrupt Control Mode Select Bit (R_SIRQMOD) 0b: Toshiba method. (Default) 1b: VESA method. 7.46 MISC1 Register |Config|NAME |RW |D7 |D6 |D5 |D4 |D3 |D2 |D1 |D0 |PCLR | |ADh |PPM1S |RW |CLKP |CLKM |- |DEMD |- |CSNC |- |RDLE |01h | D7: CLOCKRUN Control bit (CLKRUNCNT) 1b : Enable CLOCKRUNP protocol in PCI side is enabled. 0b : Disable D6: CLOCKRUN mode bit (CLKRUNMOD) 1b : Clock input is always requested when CardBus Card is inserted. 0b : Clock input is requested only when a transaction is not finished. D5: IRQ REQ mode bit 1b: Enable CLOCKRUN is requested by interruption. 0b : Disable D4: Detect REQ mode bit 1b : Enable CLOCKRUN is requested by an interruption while detecting a Card. 0b : Disable D3: EXT INT PASS mode bit 1b : Direct input mode 0b : Synchronized input mode D2: CardBus Socket Present Register Not clear 1b : Disable (Conventional compatible mode) 0b : Enable CardBus Socket Present Register is initialized. D1: CardBus Buffer Control bit (CBBUFCNT) 1b : Buffer is turned on when CardBusCard is inserted. 0b : Buffer is turned on when CardBus Card is inserted and power supply to the card is finished. D0: R2 Data Bus Low Enable bit 1b : Assert Data Bus to Low when not RW access. 0b : Conventional compatible mode. 7.47 ZV Configuration Register |Config|NAME |RW |D7 |D6 |D5 |D4 |D3 |D2 |D1 |D0 |PCLR| |AEh |PPM2S |RW |ZVPMS|- |- |- |- |- |ZVMD |R_ZVENZ |00h | D7: ZV Port Mode Select. 1b : Bus method. 0b : Multiplexer method. D1: ZV Mode Select 1b : This field enable for indicating the status of ZV Port/ D0 of ZV Control Register (Config : 9Ch) and D1 - D0 of Audio /Video Switching Register (Offset : 3Ch) indicate the status of ZV Port when read.. 0b : This field disable for indicating the status of ZV Port/ D0: R_ZVENZ 1b : DISABLE Write to 9Ch bit0 , 3Ch bit0, or1 have no sense. 0b : ENABLE Value is written in the register by writing "1" to 9Ch bit0 , 3Ch bit0 and 1. 7.48 Buffer Control Register |Config|NAME |RW |D7 |D6 |D5 |D4 |D3 |D2 |D1 |D0 |PCLR | |B0h |PPBFC |RW |- |- |- |- |WBCS3 |WBCS2 |EPLTE |IPLTE|07h | D7: Reserved "1" fixed. D6-D4: Reserved "0" fixed. D3-D2: Write Buffer Count Select bit 00b : 4 counts 01b : 8 counts 1x" : 10 counts NOTE: Default is 8 counts D1: EPLT Enable bit 1b : Latency Timer enable. (MWLT1, MWLTB, MRLT1, MRLTB, DBULT are enabled.) Delay transaction and post are enabled. 0b : Latency Timer disable.(Direct mode) Re-try is not returned to the master until the cycle for the target is completed. D0: IPLT Enable bit 1b : Latency Timer enable. (DBDLT is enabled.) Delay transaction and post are enabled. 0b : Latency Timer disable. (Direct mode) Retry is not returned to the master until the cycle for the target is completed. Two kinds of Timer Start signal for disregarding flag to PCI. NOTE: Timer counts re-try. 23 Debug Register |Config|NAME |RW |D7|D6 |D5 |D4 |D3 |D2|D1 |D0 |PCLR | |BBh |PPDBG |RW |- |CRCAE |RRCAE |ACMPT |- |- |GPORT |WTCH |00h | D7: Reserved "0" fixed D6: CB Register Config Access Enable Bit 1b : Enable CardBus Register is mapped in the configuration space. Function number of config. Access is "4" in Slot A and "5" in Slot B. 0b : Disable D5: R2 Register Config Access Enable Bit 1b : Enable R2 Register is mapped in the configuration space. Function number of config. Access is "6" in Slot A and "7" in Slot B. 0b : Disable D4: R2 Access Compatible Register 1b : IO/memory access to R2 Card timing is the same as existing model of this controller. 0b : IO/memory access to R2 Card timing is the least spec of PCCard16. (Fast access mode) D3-D2: Reserved "0" fixed.. D1: GPORT bit 1b:ZVPCLK=HI 0b:ZVPCLK=LOW D0: WATCH bit 1b:Internal signal trace mode 0b:Normal mode NOTE : R2 Card can not be used when "1". ===Internal signal and ZV output=== ZVPCLK = GPORT HRFF = A_CBM VSYNC = B_CBM Y (7) = DBD_DTIN UV (7) = A_VREQZ Y (6) = DBU_DTIN UV (6) = B_VREQZ Y (5) = MWB_DTIN UV (5) = A_VGNTZ Y (4) = MRB_DTIN UV (4) = B_VGNTZ Y (3) = IPTS_DTIN UV (3) = CB_A_MX Y (2) = EPTS_DTIN UV (2) = CB_B_MX Y (1) = IPMS_DTIN UV (1) = R2_A_MX Y (0) = EPMS_DTIN UV (0) = R2_B_MX 24 Serial Power Control Register |Config|NAME |RW |D7|D6|D5 |D4 |D3 |D2 |D1 |D0 |PCLR | |BEh |PPSPCWR |RW |- |- |SCLK |SLT |SOFL |SMOD |SCKMD |SPEN |03h | D7-6: Reserved RW enabled. D5: SPWRCLK 1b: 32 X PCICLK 0b: 1 X PCICLK D4: SPWRLT 1b: Half-CLOCK timing 0b: CLOCK sync timing D3: PWROFL 1b:Hi-z 0b:0v D2: PWRMOD 1b: MICREL MIC2546 mode 0b: TI TPS2216/14 mode D1: PWRCKMOD 1b: Input mode 32kHz CLOCK is input to CLOCK/CLK32 terminal. 0b: Output mode Serial Bus Logic set in D5 is output. D0: SPWREN 1b: Serial Power Mode Power control - Serial mode ISA_IRQ parallel output is enabled. 0b: Parallel Power Mode Power control - Parallel mode ISA_IRQ parallel mode is disabled. 25 IRQ Routing Register |Config|NAME |RW |D31 |D30 |D29 |D28 |D27 |D26 |D25 |D24 |PCLR | |C0h |IRQRTG |R/W|IRQMUX7 |IRQMUX6 |0000h| | | | | | | | | | | | | |0000h| | | | |D23 |D22 |D21 |D20 |D19 |D18 |D17 |D16 | | | | | |IRQMUX5 |IRQMUX4 | | | | | |D15 |D14 |D13 |D12 |D11 |D10 |D9 |D8 | | | | | |IRQMUX3 |IRQMUX2 | | | | | |D7 |D6 |D5 |D4 |D3 |D2 |D1 |D0 | | | | | |IRQMUX1 |IRQMUX0 | | D31-D28: IRQMUX7 Routing Assign one of the 12 interrupts (SMI,IRQ3, 4,5,7,9,10,11,12,14,15) to IRQMUX7. D27-D24: IRQMUX6 Routing Assign one of the 12 interrupts (SMI, IRQ3,4,5,7,9,10,11,12,14,15) to IRQMUX6. D23-D20: IRQMUX5 Routing Assign one of the 12 interrupts (SMI, IRQ3, 4,5,7,9,10,11,12,14,15) to IRQMUX5. D19-D16: IRQMUX4 Routing Assign one of the 13 interrupts (SMI, RIOUT, IRQ3, 4,5,7,9,10,11,12,14,15) to IRQMUX4. D15-D12: IRQMUX3 Routing Assign one of the 12 interrupts (RIOUT, IRQ3, 4,5,7,9,10,11,12,14,15) to IRQMUX3. D11-D8: IRQMUX2 Routing Assign one of the 12 interrupts (SMI, IRQ3, 4,5,7,9,10,11,12,14,15) to IRQMUX2. D7-D4: IRQMUX1 Routing Assign one of the 12 interrupts (SMI, IRQ3, 4,5,7,9,10,11,12,14,15) to IRQMUX1. D3-D0: IRQMUX0 Routing Assign one of the 13 interrupts (INTB, SMI, IRQ3, 4,5,7,9,10,11,12,14,15) to IRQMUX0. |Routing |IRQMUX7|IRQMUX6 |IRQMUX5 |IRQMUX4 |IRQMUX3 |IRQMUX2 |IRQMUX1 |IRQMU| |bit | | | | | | | |X0 | |0000b |No IRQ Routing | |0001b |No IRQ Routing |RIOUT |RIOUT |No IRQ Routing |INTB | |0010b |SMI | |0011b |IRQ3 | |0100b |IRQ4 | |0101b |IRQ5 | |0110b |No IRQ Routing | |0111b |IRQ7 | |1000b |No IRQ Routing | |1001b |IRQ9 | |1010b |IRQ10 | |1011b |IRQ11 | |1100b |IRQ12 | |1101b |No IRQ Routing | |1110b |IRQ14 | |1111b |IRQ15 | 26 Additional Control Register This register is for internal signal trace. Only one is existence in this controller. (A, B common register) |Config|NAME |RW |D7 |D6 |D5 |D4 |D3 |D2 |D1 |D0 |PCLR | |C4h |NVADC |R |- |- |- |- |- |- |SACTS |PSSPS |00h | D7-2: Reserved 0b : fixed. D1: Socket Activity Status Bit 1b : Card Socket is Active. Access from PC Card is enabled. 0b : Card Socket is not non-Active. Access from PC Card is disabled. D0: Power Stream in Progress Status Bit 1b : Enable Instruction to Card Slot Power Switch is enabled. 0b : Disable Instruction to Card Slot Power Switch is disabled. 27 Configuration Control Register This register controls Configuration Register and interrupt. Only one exists in this controller. (A, B common register) |Confi|NAME |RW|D31 | | | | | | |D16 |PCLR | |g | | | | | | | | | | | | |FCh |PPCNF |RW|- | | | | | | |- |0000h | | | | |D15 |D14 |D13 |D12 |D11 |D10 |D9 |D8 |PCLR | | | | |IR15LE|IR14LE|IR12LE|IR11L|IR10LE|IR9LE|IR7LE|IR6LE|00h | | | | | | | |E | | | | | | | | | |D7 |D6 |D5 |D4 |D3 |D2 |D1 |D0 |PCLR | | | | |IR5LE |IR4LE |IR3LE |- |SIROE |DSKST|SIRMS|IDWE |00h | D31-D16: Reserved 0b : fixed D15: IRQ15 Level/Edge Select bit This bit selects Edge Trigger or Level Trigger of IRQ15 at serial interrupt transmission. 0b : Edge Trigger 1b : Level Trigger D14: IRQ14 Level/Edge Select bit This bit selects Edge Trigger or Level Trigger of IRQ14 at serial interrupt transmission. 0b : Edge Trigger 1b : Level Trigger D13: IRQ12 Level/Edge Select bit This bit selects Edge Trigger or Level Trigger of IRQ12 at serial interrupt transmission. 0b : Edge Trigger 1b : Level Trigger D12: IRQ11 Level/Edge Select bit This bit selects Edge Trigger or Level Trigger of IRQ11 at serial interrupt transmission. 0b : Edge Trigger 1b : Level Trigger D11: IRQ10 Level/Edge Select bit This bit selects Edge Trigger or Level Trigger of IRQ10 at serial interrupt transmission. 0b : Edge Trigger 1b : Level Trigger D10: IRQ9 Level/Edge Select bit This bit selects Edge Trigger or Level Trigger of IRQ 9 at serial interrupt transmission. 0b : Edge Trigger 1b : Level Trigger D9: IRQ7 Level/Edge Select bit This bit selects Edge Trigger or Level Trigger of IRQ 7 at serial interrupt transmission. 0b : Edge Trigger 1b : Level Trigger D8: IRQ6 Level/Edge Select bit This bit selects Edge Trigger or Level Trigger of IRQ 6 at serial interrupt transmission. 0b : Edge Trigger 1b : Level Trigger D7: IRQ5 Level/Edge Select bit This bit selects Edge Trigger or Level Trigger of IRQ 5 at serial interrupt transmission. 0b : Edge Trigger 1b : Level Trigger D6: IRQ4 Level/Edge Select bit This bit selects Edge Trigger or Level Trigger of IRQ 4 at serial interrupt transmission. 0b : Edge Trigger 1b : Level Trigger D5: IRQ3 Level/Edge Select bit This bit selects Edge Trigger or Level Trigger of IRQ 3 at serial interrupt transmission. 0b : Edge Trigger 1b : Level Trigger D4: Reserved 0b : fixed D3: Serial Interrupt Output Enable bit This bit is an output enable bit of the serial interrupt signal of this controller. 0b : The serial interrupt signal of is disabled. However, the clock for serial interrupt is received and keep synchronized. 1b : The output of the serial interrupt signal is enabled. When this bit changes to 1b (Permission) from 0b (stop), interrupts which had collected by then is cleared. D2: Deskstation Type bit 0b : DeskStation9 can be connected. 1b : DeskStation8 can be connected. D1: Serial Interrupt Mode Select bit This bit selects serial interrupt mode. 0b : New Serial Interrupt Mode. (New : Receive Rising Edge or Break Edge, or receive Level) 1b : Conventional Serial Interrupt Mode. (Conventional : Receive only Rising Edge.) D0: ID register Write Enable bit 1b: Enable Write is enabled for the following Configuration Register. Vendor ID (Offset:00h) Device ID (Offset: 02h) Status ID (Offset: 06h:bit4) Revision ID (Offset: 08h) Class Code (Offset: 09h) Subsystem Vender ID Register (Offset: 40h) Subsystem Device ID Register (Offset: 42h) Power Management Capabilities Register (Offset: 82h:bit15, 5- 3) Power Management Control/Status Register (Offset: 84h:bit14-13) PMCSR PCI to CardBus Bridge Support Extensions Register (Offset: 86h:bit7-6) Data Register (Offset: 87h) 0b: Disable Read only. PC-Card16 Register This controller has Register Set for PC-Card16 cards. Access to Register Sets is enabled after Slot Control Register - SLOTENbit (Config.Reg. A0h - D6) is activated. (=1) (Address decoding is started.) Register sets are mapped by the 2 K byte space on the memory space of a system which starts from the address which added 2 K bytes (800h) of offset to the base address hold Base Address Register (Config.offset: 10h). 8.1 Identification and Revision Register |Offset|Offset|NAME |RW |D7 |D6 |D5 |D4 |D3 |D2 |D1 |D0 |PCLR | |00h |800 |PPRVN |RW |ID1|ID0|- |- |REV3 |REV2 |REV1 |REV0 |00h | D7-D6: PCMCIA Card Type ID D3-D0: Revision This register does not affect PC Card. This register can write when D4 (Slot Control Register (Config: A0h)) is set to 0. (Ref.) The controller of EXCA compatible by Intel can read 83h when reading this register. (B- step compliant of EXCA) A-step compliant can read 82h. 8.2 Interface Status Register Description in parentheses is a terminal name when selecting I/O Card Interface (Offset 03h, D5 = 1) This register is read only, and the status of each terminal can be seen as register data. This register does not affect performance of this controller. Data is latched at Break Edge of IORD#, and the data is read so that the read data may not change to the change in a read cycle. As to BVD2?Ready/Busy?Write Protect , it is fixed to HI when the card is not inserted because of the internal gate. Reserved bit of D7 can always read H1. Card Power Active bit of D6 can read the status of a power supply of the card. (1 at the time of power supply impression) |Offset|Offset|NAME |RW |D7|D6 |D5 |D4 |D3 |D2 |D1 |D0 |PCLR | |01h |801 |PPIFS|R |- |CPA |BSY# |WP |CD2# |CD1# |BVD2 |BVD1 |- | D7: Reserved (1b fixed) D6: Card Power Active 1b : Card Power Supply (5V) provided. 0b : Card Power Supply (5V) not provided. D5: BSY# Status Indicate the status of an external input signal BSYA#/BSYB#. D4: WP Status Indicate the status of an external input signal WPA/WPB. D3: CD2# Status Indicate the status of an external input signal CD2A#/CD2B#. D2: CD1# Status Indicate the status of an external input signal CD1A#/CD1B#. D1: BVD2 Status Indicate the status of an external input signalBVD2A/BVD2B. D0: BVD1 Status Indicate the status of an external input signal BVD1A/BVD1B. Indicate 1 when BSY#, WP and BVD2 Card are not inserted. 8.3 Power Control Register |Offset|Offset|NAME |RW |D7 |D6 |D5 |D4 |D3 |D2|D1 |D0 |PCLR| |02h |802 |PPPCN |RW |COE |DRCL |EAPS |CP5E |CP3E |- |VPP1|VPP0|00h | D7: Output Enable Enable/Disable of I/F signal for the following cards. CE1#, CE2#, OE#, WE#/PGM#, IORD#, IOWR#, REG#, RESET, A25-00, D15-00 1b: Enable 0b: Disable (Hi-z) D6: Disable Resume Reset 0b: Enable CARD 16 Reg. is initiated by Resume Reset. 1b: Disable CARD 16 Reg. maintain the value when Resume Reset. All the registers of PC-Card16 are the subject to reset to SUPEND/RESUME. D5: Auto Power Switch enable 0b: Enable Card Power Supply enabled with/without the card is put in. 1b: Disable Card Power Supply disabled without the card is put in. D4: Card Power Enable (1) 0b: Card Power Supply disabled. 1b: Card Power Supply enabled. However, when this bit is "1" but D5 is "1" AND the card is not inserted in the slot, power supply to the slot is disabled. D3: Card Power Enable (0) This bit is invalid when ToPIC100 Function Control Register (Card16.3Eh) bit 0 (Power Control Enable) is 0. RW possible register. When The ToPIC100 Function Control Register (3Eh) bit 0 (Power Control Enable) is 1 AND D4 is 1, Power Control Terminal will change to output the voltage as follows. 1b: 3v 0b: 5v However, when D4 is 1, D5 is 1 AND the card is not inserted in the slot, Power Supply is disabled. |Card Power |Power Control Register | | |Enable | | | |3Eh D0 |D4 |D3 |Power Supply | | | | |Mode | |0 |0 |- |0 v | |0 |1 |- |5 v | |1 |0 |- |0 v | |1 |1 |0 |5 v | |1 |1 |1 |3 v | *D4, 3 compatible with 82092AA. D2: Reserved RW possible. No affect to this controller. D1-D0: VPP Control Bit1-0 Slot Power Supply (VPP) controlled. |D1 |D0 |VPP Power Supply | | | |Mode | |0 |0 |0.0 v | |0 |1 |VCC | |1 |0 |12 v | |1 |1 |Reserved | D4, D1, D0 and Card Power Supply Card Power Supply signal changes its output signal as follows with the setting of PWRSIGS1 signal. ToPIC100 Function Control Register (Card16. 3Eh) D0=0 |CARD |Power Control Register |Power Supply | |ON* |(Offset:02h) |Provided | | |D5 |D4 |D3 |D1 |D0 |VCC |VPP | |X |X |0 |X |X |X |0 |0 | |X |0 |1 |X |0 |0 |5 |0 | | | | | |0 |1 | |5 | | | | | |1 |0 | |12 | | | | | |1 |1 | |0 | |1 |1 |1 |X |0 |0 |5 |0 | | | | | |0 |1 | |5 | | | | | |1 |0 | |12 | | | | | |1 |1 | |0 | |0 |1 |1 |X |X |X |0 |0 | ToPIC100 Function Control Register (3Eh) D0=1 |CARD | Power Control Register |Power Supply | |ON* |(Offset:02h) |Provided | | |D5 |D4 |D3 |D1 |D0 |VCC |VPP | |X |X |0 |X |X |X |0 |0 | |X |0 |1 |0 |0 |0 |5 |0 | | | | | |0 |1 | |5 | | | | | |1 |0 | |12 | | | | | |1 |1 | |0 | |X |0 |1 |1 |0 |0 |3.3 |0 | | | | | |0 |1 | |3.3 | | | | | |1 |0 | |12 | | | | | |1 |1 | |0 | |1 |1 |1 |0 |0 |0 |5 |0 | | | | | |0 |1 | |5 | | | | | |1 |0 | |12 | | | | | |1 |1 | |0 | | |1 |1 |1 |0 |0 |3.3 |0 | | | | | |0 |1 | |3.3 | | | | | |1 |0 | |12 | | | | | |1 |1 | |0 | |0 |1 |1 |X |X |X |0 |0 | *CARD ON indicates the status which that Card put in when set to 1. 8.4 Interrupt and General Control Register |Offset|Offset|NAME |RW |D7 |D6 |D5 |D4 |D3 |D2 |D1 |D0 |PCLR | |03h |803 |PPICN |RW |ERI|CRST |CTYP |ESMI|PIR3|PIR2|PIR1|PIR0|00h | D7: Ring Indicate Enable 1b: Enable STSCHG signal output from PIN "RIOUT" (I/O Card Mode) 0b: Disable Always read "0" in CARD16 Reg. 04h-D0. D6: Card Reset Reversal of 0b/1b set in this bit is output from CRESET terminal. CRESET signal is activated when setting 0. (Soft Reset) D5: Card Type 1b: I/O Card Mode 0b: Memory Card Mode D4: SMI Enable 1b: Assign "SMI" (output from PIN"IRQDTZ" at SMI timing of serial INT) 0b: Assign "IRQX" (output from PIN"IRQDTZ" at IRQX timing of serial INT) D3-D0: I/O IRQ Bit 3-0) This bit is for mapping the input from IREQ terminal at I/O Card IF Mode to IRQ of the system. In the following table, when setting to Reserved, same performance as IRQ Not Selected. |D3 |D2 |D1 |D0 |IRQ LEVEL | |0 |0 |0 |0 |IRQ Not Selected | |0 |0 |0 |1 |Reserved | |0 |0 |1 |0 |Reserved | |0 |0 |1 |1 |IRQ3 Enable | |0 |1 |0 |0 |IRQ4 Enable | |0 |1 |0 |1 |IRQ5 Enable | |0 |1 |1 |0 |Reserved | |0 |1 |1 |1 |IRQ7 Enable | |1 |0 |0 |0 |Reserved | |1 |0 |0 |1 |IRQ9 Enable | |1 |0 |1 |0 |IRQ10 Enable | |1 |0 |1 |1 |IRQ11 Enable | |1 |1 |0 |0 |IRQ12 Enable | |1 |1 |0 |1 |Reserved | |1 |1 |1 |0 |IRQ14 Enable | |1 |1 |1 |1 |IRQ15 Enable | 5. Card Status Change Register This register is read only, and holds the status of change for Card Status Signal. However, write operation may have an affection. (Refer to the following register clear method) When Card Status Signal set as enabled by Card Status Change Control Register (Card16. 05h) has changes, "1" is set to the bit related to this register. And interrupt occurs from IRQ line simultaneously, which selected by CSC IRQ Bit 3-0. ( or SMI occurs) A disabled bit set by Card Status Change Control Register (Card16. 05h) has no "1" even if the related status signal has a change. Two methods in clearing the "1" bit in this register. If D2=0 (Global Control Register (Card16. 1Eh)), D3 - D0 having "1" will be cleared and IRQ line (or SMI) becomes inactive only by reading this register. When D2=1 (Global Control Register), it's not cleared by reading. It can be cleared by writing "1" to the bit. (Write Back Mode) Since every 1 bit can be cleared, all bits have to be cleared to inactivate IRQ line (or SMI). |Offset|Offset|NAME |RW |D7 |D6 |D5 |D4|D3 |D2 |D1 |D0 |PCLR | |04h |804 |PPCSC |R |- |- |- |- |CDC |RDYC |BATW |BATD |00h | D3: Card Detect Change 1: Changed 0: Not changed Set up when CD1 terminal and CD2 terminal are changed from "LL" to "LH" or "HL" (Detected the Card pulled out) , or are changed from "HH" to "LL" (Detected the Card is put in). But cannot be sensed as to Detect during suspended. This bit can set the status same with the Card (Software Card Detect) actually inserted or removed by writing "1" to D5 (Soft Wear Card Detect Interrupt) of Additional General Control Register (Offset 16h). It is effective only when D3 of Card Status Change Control Register (Offset 05h) is "1", and it does not change when D3 is "0". Software Card Detect is also invalid. D2: Ready Change) 1: Changed Card status Change Interrupt will occur due to RDY/#BSY signal switched to "H" form "L" in case of Memory Card IF. Set up once, or never be 0 even if returned to "L". 0: Not changed In either case of Memory Card whose status is not changed or I/O Card. D1: Battery Warning 1: Battery Warning Set up in case of Memory Card Battery Warning (an external input signal BVD1A/BVD1B and BVD2A/BVD2B are changed from "HH" from "HL"). Set up once, or never be 0 even if returned to Battery Good ("HH"). When BVD1A is changed to "L" (Battery Dead), this bit will be cleared. 0: Not Battery Warning In either case of Battery Warning whose status is not changed or I/O Card. D0: Battery Dead 1: Battery Dead Set up in case of Memory Card, and when Battery Good status or Battery Warning switched to Battery Dead status (an external input signal BVD1A/BVD1B is changed to "L", and Card Status Change Interrupt will occur. Set up once, or never be 0 even if returned to Battery Good ("H") or Battery Warning. 0: Not Battery Dead In either case of Battery Dead whose status is not changed or I/O Card. Bit is reset by following way in this Register (=0). This register reads when D2 (Global Control Register (Offset: 1Eh)) is set to 0. 1 will be written to each bit when D2 (Global Control Register) is set to 1. After Card- Put in, D2-D0 will not be sensed between 1ms. 8.6 Card Status Change Interrupt Control Register |Offset|Offset|NAME |RW |D7 |D6 |D5 |D4 |D3 |D2 |D1 |D0 |PCLR| |05h |805 |PPCSI|RW |CIR3|CIR2|CIR1|CIR0|ECDD |ERCH |EBAW |EBAD|00h | D7-D4: CSC IRQ Bit 3-0 Assigns the interrupt by Card Status Change to PIC interrupt input. D3: Card Detect Enable 1b: Enable Interrupt by Card Detect Change enabled. 0b: Disable interrupt by Card Detect Change disabled. D2: Ready Enable 1b: Enable Interrupt by READY Change enabled. 0b: Disable Interrupt by READY Change disabled. Ready Change Detect is always disabled in case of I/O Card IF. D1: Battery Warning Enable 1b: Enable Interrupt by BATTERY WARNING enabled. 0b: Disable Interrupt by BATTERY WARNING disabled. In case of interrupt by BATTERY WARNING enabled, CSC INT (or SMI) will occur when BVD2 signal is changed to "L" from "H". BATTERY WARNING Detect is always disabled in case of I/O Card IF. D0: Battery Dead Enable / (STSCHG# Enable) 1: Enable Interrupt by BATTERY DEAD enabled. 0: Disable Interrupt by BATTERY DEAD disabled. In case of interrupt by BATTERY DEAD enabled, CSC INT (or SMI) will occur when BVD1 signal is changed to "L" from "H". BATTERY DEAD Detect is always disabled in case of I/O Card IF. D7-D4 (CSC IRQ Bit3-0) and IRQ** |D7 |D6 |D5 |D4 |IRQ LEVEL | |0 |0 |0 |0 |IRQ Not Selected | |0 |0 |0 |1 |Reserved | |0 |0 |1 |0 |Reserved | |0 |0 |1 |1 |IRQ3 Enable | |0 |1 |0 |0 |IRQ4 Enable | |0 |1 |0 |1 |IRQ5 Enable | |0 |1 |1 |0 |Reserved | |0 |1 |1 |1 |IRQ7 Enable | |1 |0 |0 |0 |Reserved | |1 |0 |0 |1 |IRQ9 Enable | |1 |0 |1 |0 |IRQ10 Enable | |1 |0 |1 |1 |IRQ11 Enable | |1 |1 |0 |0 |IRQ12 Enable | |1 |1 |0 |1 |Reserved | |1 |1 |1 |0 |IRQ14 Enable | |1 |1 |1 |1 |IRQ15 Enable | 8.7 Window Enable Register |Offset|Offset|NAME |RW|D7 |D6 |D5|D4 |D3 |D2 |D1 |D0 |PCLR| |06h |806 |PPWEN |RW|IOW1|IOW0 |- |MEW4 |MEW3 |MEW2 |MEW1 |MEW0 |00h | D7: I/O Window 1 Enable 1b: Card I/O WINDOW 1 Enable I/O Access within the address limit specified by Offset 0Ch- Offset 0Fh is I/O Access to the Card. CPU address is output directly for A15-00 and ALL0 for A25-16. 0b: Card I/O WINDOW 1 Disable I/O access cycle does not occur even if I/O access from within the address limit specified by Offset 0Ch-Offset 0Fh. D6: I/O Window 0 Enable 1b: Card I/O WINDOW 0 Enable I/O Access within the address limit specified by Offset 08h- Offset 0Bh is I/O Access to the Card. CPU address is output directly for A15-00 and ALL0 for A25-16. 0b: Card I/O WINDOW 0 Disable I/O Access cycle does not occur even if I/O Access from within the address limit specified by Offset 08h-Offset 0Bh. D4: Memory Window 4 Enable 1b: Card MEMORY WINDOW 4 Enable Memory Access within the address limit specified by Offset 30h- Offset 33h will be Memory Access to the Card. In this case, CPU address is output directly for A11-00, and A25-12 will be added the value of Offset specified by the Register (34h, 35h). 0b: Card MEMORY WINDOW 4 Disable Memory Access Cycle does not occur even if Memory Access is from within the address limit specified by Offset 30h-Offset 33h. D3: Memory Window 3 Enable 1b: Card MEMORY WINDOW 3 Enable Memory Access within the address limit specified by Offset 28h-Offset 2Bh will be Memory Access to the Card. In this case, CPU address is output directly for A11-00, and A25-12 will be added the value of Offset specified by the Register. (2Ch, 2Dh) 0b: Card MEMORY WINDOW 3 Disable Memory Access does not occur even if Memory Access is from within the address limit specified by Offset 28h-Offset 2Bh. D2: Memory Window 2 Enable 1b: Card MEMORY WINDOW 2 Enable Memory Access within the address limit specified by Offset 20h-Offset 23h will be Memory Access to the Card. In this case, CPU address is output directly for A11-00, and A25-12 will be added the value of Offset specified by the Register. (24h, 25h) 0b: Card MEMORY WINDOW 2 Disable Memory Access Cycle does not occur even if Memory Access is from within the address limit specified by Offset 20h- Offset 23h. D1: Memory Window 1 Enable 1b: Card MEMORY WINDOW 1 Enable Memory Access within the address limit specified by Offset 18h-Offset 1Bh will be Memory Access to the Card. In this case, CPU address is output directly for A11-00, and A25-12 will be added the value of Offset specified by the Register. (1Ch, 1Dh) 0b: Card MEMORY WINDOW 1 Disable Memory Access Cycle does not occur even if Memory Access is from within the address limit specified by Offset 18h- Offset 1Bh. D0: Memory Window 0 Enable 1b: Card MEMORY WINDOW 0 Enable Memory Access within the address limit specified by Offset 10h-Offset 13h will be Memory Access to the Card. In this case, CPU address is output directly for A11-00, and A25-12 will be added the value of Offset specified by the Register. (14h, 15h) 0b: Card MEMORY WINDOW 0 Disable Memory Access Cycle does not occur even if Memory Access is from within the address limit specified by Offset 10h- Offset 13h. 8. I/O Window Control Register |Offset|Offse|NAME |RW |D7 |D6 |D5 |D4 |D3 |D2 |D1 |D0 |PCLR| | |t | | | | | | | | | | | | |07h |807 |PPWCN |RW |I11|I1ZW|I1SR|I1DS |IO16|I0ZW|IOSR|IODS|00h | | | | | |6 | | | | | | | | | D7: I/O Window 1 Wait State Sets up the Number of 16bit I/O Access cycle in I/O Window 1. 1b: 4 ISA CLOCK (1WAIT) MODE 0b: STANDARD BUS CYCLE (3 ISA CLOCK) While WAIT signal from the Card is active, the Wait Cycle is inserted further and Bus Cycle is extended. (WAIT form the Card is prioritized.) D6: I/O Window 1 Zero Wait State Sets up the Number of 8bit I/O Access Cycle in I/O Window 1. 1b: 4 ISA CLOCK (0 WAIT) MODE 0b: STANDARD BUS CYCLE (6 ISA CLOCK) When WAIT signal from the Card is active (L), 0 Wait Cycle does not occur. (WAIT form the Card is prioritized) D5: I/O Window 1 -IOIS16 Source Sets up the Data Length of I/O Access in I/O Window 1. 1b: External Input Signal "IOIS16#". 0b: Internal Output Signal PCM_I16Z (16bit I/O) enabled (=0) when D4 is set to 1. D4: I/O Window 1 Data Size Set up the I/O Access Length in I/O Window 1 when D5=0. 1b: 16bit Access (Enabled when I1SR is set to 0) 0b: 8bit Access D3: I/O Window 0 Wait State Set up 16bit I/O Access Cycle Number in I/O Window 0. 1b: 4 ISA CLOCK (1WAIT) MODE 0b: STANDARD BUS CYCLE (3 ISA CLOCK) While WAIT signal from the Card is active, the Wait Cycle is inserted further and Bus Cycle is extended. (c.) D2: I/O Window 0 Zero Wait State Sets up 8bit I/O Access Cycle Number in I/O Window 0. 1b: 4 ISA CLOCK (0 WAIT) MODE 0b: STANDARD BUS CYCLE (6 ISA CLOCK) When WAIT signal from the Card is active (LOW), 0 Wait Cycle does not occur. (WAIT from the Card is prioritized.) D1: I/O Window 0 -IOIS16 Source Sets up the Data Length of I/O Access in I/O Window 0. 1b: External Input Signal "IOIS16#". 0b: Register Sets up (D4) D0: I/O Window 0 Data Size Set up the I/O Access Length in I/O Window 0 when D5=0. 1b: 16bit Access 0b: 8bit Access Disabled when D5=1. 8.9 I/O Window 0 Start Low Address Register |Offset|Offset|NAME |RW |D7 |D6 |D5 |D4 |D3 |D2 |D1 |D0 |PCLR | |08h |808 |PPI0S |RW |I0S|I0S|I0S|I0S|I0S|I0S|I0S|I0S|00h | | | | | |7 |6 |5 |4 |3 |2 |1 |0 | | D7-D0: Address 7-0 Set up the start lower 8bit, which has I/O access to the Card in I/O Window 0. 8.10 I/O Window 0 Start High Address Register |Offset|Offset|NAME |RW |D7 |D6 |D5 |D4 |D3 |D2 |D1 |D0 |PCLR | |09h |809 |PPI0S |RW |I0S|I0S|I0SD|I0S|I0S|I0S|I0S|I0S|00h | | | | | |F |E | |C |B |A |9 |8 | | D7-D0: Address 8-15 Set up the start upper 8bit, which has I/O access to the Card in I/O Window 0. 8.11 I/O Window 0 Stop Low Address Register |Offset|Offset|NAME |RW |D7 |D6 |D5 |D4 |D3 |D2 |D1 |D0 |PCLR | |0Ah |80A |PPI0E |RW |I0E|I0E|I0E|I0E|I0E|I0E|I0E|I0E|00h | | | | | |7 |6 |5 |4 |3 |2 |1 |0 | | D7-D0: I/O Window 0 Stop Address 7-0 Set up Stop Address lower 8bit, which has I/O access to the Card in I/O Window 0. 8.12 I/O Window 0 Stop High Address Register |Offs|Offse|NAME |RW |D7 |D6 |D5 |D4 |D3 |D2 |D1 |D0 |PCLR | |et |t | | | | | | | | | | | | |0Bh |80B |PPI0E|RW |I0E|I0EE|I0ED|I0EC|I0EB|I0EA |I0E9|I0E|00h | | | | | |F | | | | | | |8 | | D7-D0: I/O Window 0 Stop Address 15-8 Set up the Stop Address upper 8bit, which has I/O access to the Card in I/O Window 0. 8.13 I/O Window 1 Start Low Address Register |Offset|Offset|NAME |RW |D7 |D6 |D5 |D4 |D3 |D2 |D1 |D0 |PCLR | |0Ch |80C |PPI1S |RW |I1S|I1S|I1S|I1S|I1S|I1S|I1S|I1S|00h | | | | | |7 |6 |5 |4 |3 |2 |1 |0 | | D7-D0: Address 7-0 Set up the start lower address 8bit, which has I/O access to the Card in I/O Window 1. 8.14 I/O Window 1 Start High Address Register |Offset|Offset|NAME |RW |D7 |D6 |D5 |D4 |D3 |D2 |D1 |D0 |PCLR | |0Dh |80D |PPI1S |RW |I1SF|I1S|I1SD|I1S|I1S|I1S|I1S|I1S|00h | | | | | | |E | |C |B |A |9 |8 | | D7-D0: Address 8-15 Set up the start address upper 8bit, which has I/O access to the Card in I/O Window 1. 8.15 I/O Window 1 Stop Low Address Register |Offset|Offset|NAME |RW |D7 |D6 |D5 |D4 |D3 |D2 |D1 |D0 |PCLR | |0Eh |80E |PPI1E |RW |I1E|I1E|I1E|I1E|I1E|I1E|I1E|I1E|00h | | | | | |7 |6 |5 |4 |3 |2 |1 |0 | | D7-D0: Address 7-0 Set up the stop address lower 8bit, which has I/O access to the Card in I/O Window 1. 8.16 I/O Window 1 Stop High Address Register |Offset|Offset|NAME |RW |D7 |D6 |D5 |D4 |D3 |D2 |D1 |D0 |PCLR | |0Fh |80F |PPI1E |RW |I1EF|I1EE|I1ED|I1EC|I1EB|I1E|I1E|I1E|00h | | | | | | | | | | |A |9 |8 | | D7-D0: Address 8-15 Set up the stop address upper 8bit, which has I/O access to the Card in I/O Window 1. 8.17 Memory Window 0 Start Low Address Register |Offs|Offs|NAME |RW |D7 |D6 |D5 |D4 |D3 |D2 |D1 |D0 |PCLR| |et |et | | | | | | | | | | | | |10h |810 |PPM0S |RW |MS19|MS18|MS17|MS16|MS15|MS14|MS13|MS12 |00h | D7-D0: Address 12-19 Set up the start address lower 8bit, which has memory access to the Card in System Memory Window 0. 18. Memory Window 0 Start High Address Register This Register sets up the start address upper 4bit in Memory Window 0, and assigns data size of Memory Window and Wait control. |Offs|Offs|NAME |RW |D7 |D6 |D5 |D4 |D3 |D2 |D1 |D0 |PCLR | |et |et | | | | | | | | | | | | |11h |811 |PPM0S|RW |M0DS |M0ZW |- |- |MS23|MS22|MS21 |MS20 |00h | D7: Data Size 1b: 16bit access 0b: 8bit access D6: Zero_WS Set up the Number of Memory Access cycle. | |D6=0 |D6=1 | |8bit |Standard Cycle |0 WAIT Cycle | |MEMORY |( 6 SYS CLK ) |( 4 SYS CLK ) | |ACCESS | | | |16bit |CARD16 REG. |0 WAITCycle | |MEMORY |13H- D7, D6 |( 2 SYS CLK ) | |ACCESS | | | When WAIT signal is input from the Card, 0 Wait cycle does not occur even if this bit is set to 1. (WAIT signal from the Card is priority) D5-D4: Scratch Bit Given value can be set. No affect to this controller. R/W is possible. Scratch Bit is given name by the Spec of Exca by Intel. D3-D0: Address 20-23 Set up the start address upper 4bit, which has memory access to the Card in System Memory Window 0. 8.19 Memory Window 0 Stop Low Address Register |Offs|Offs|NAME |RW |D7 |D6 |D5 |D4 |D3 |D2 |D1 |D0 |PCLR| |et |et | | | | | | | | | | | | |12h |812 |PPM0E |RW |ME19|ME18|ME17|ME16|ME15|ME14|ME13|ME12|00h | D7-D0: Address 12-19 Set up the stop address lower 8bit, which has memory access to the Card in System Memory Window 0. 8.20 Memory Window 0 Stop High Address Register |Offs|Offs|NAME |RW |D7 |D6 |D5 |D4 |D3 |D2 |D1 |D0 |PCLR | |et |et | | | | | | | | | | | | |13h |813 |PPM0E|RW |W0S1|W0S0|- |- |MS23|MS22 |MS21 |MS20 |00h | D7-D6: Wait State Bit 1-0 / Memory Timing Select 2-1 Set up the cycle number of 16bit Memory Access. 0 0b: 3ISA Clock 0 1b: 4ISA Clock (1 Wait) 1 0b: 5ISA Clock (2 Wait) 1 1b: 6ISA Clock (3 Wait) D5-D4: Reserved RW possible. D3-D0: Memory Window 0Stop Address 23-20 Set up the stop address upper 4bit, which has memory access to the Card in System Memory Window 0. 8.21 Memory Window 0 Offset Low Address Register |Offs|Offs|NAME |RW |D7 |D6 |D5 |D4 |D3 |D2 |D1 |D0 |PCLR| |et |et | | | | | | | | | | | | |14h |814 |PPM0O |RW |MO19|MO18|MO17|MO16|MO15|MO14|MO13|MO12|00h | D7-D0: Address 12-19 Set up the offset address lower 8bit, which has memory access to the Card in System Memory Window 0. 22. Memory Window 0 Offset High Address Register Set up offset address lower 8bit of Memory Window 0. |Offs|Offs|NAME |RW |D7 |D6 |D5 |D4 |D3 |D2 |D1 |D0 |PCLR| |et |et | | | | | | | | | | | | |15h |815 |PPM0O |RW |E0WP|E0RG|MO25|MO24|MO23|MO22|MO21|MO20|00h | D7: Write Protected 1b: Disable 0b: Enable Memory write enabled. This bit is not affected by memory card. D6: -REG Active 1b: Enable REG#=0. Access via System Memory Window will result in attribute memory. 0b: Disable REG#=1. Access via System Memory Window will result in common memory. D5-D0: Address 20-25 Set up the offset address upper 6bit, which has memory access to the Card in System Memory Window 0. 8.23 Additional General Control Register This Register is added by ExCAB-STEP by Intel. |Offset|Offset|NAME |RW |D7 |D6 |D5 |D4 |D3 |D2 |D1 |D0 |PCLR | |16h |816 |PPACN |RW |VS2|VS1|SWD |- |- |- |CRR |- |00h | D7: Voltage Sense2 Status Indicate the status of an external input signal VS2A/VS2B when D1 (Function Register Offset : 3Eh) is set to 1b. D6: Voltage Sense1 Status Indicate the status of an external input signal VS1A/VS1B when D1 (Function Register Offset : 3Eh) is set to 1b. D5: (S/W Card Detect Interrupt) - Read Zero Writing "1" to this bit when Card Status Change Interrupt Control Register - Card Detect Enable (CARD16 REG. 05H-D3) = 1 (Detection of the Card inserted / removed is permitted) occurs Card Status Change Interrupt while sets up 1 in D3 (Card Detect Change) of Card Status Change Register, Offset 04h. It is called Software Card Detect function that makes to look like there have been inserted / removed of the Card by the Software. Software Card Detect Interrupt by this bit is completely equivalent to Card Detect Change Interrupt by insert / removal of the Card in hardware-wise. This function is invalid when D3 (Offset 05h, Card Status Change Interrupt Control Register) is set to 0. The Register bit does not exist in hardware-wise, and always can 0b when read even if 1 is written. D4-D2: Reserved R/W possible. D1: Card Removal Reset 1b: Register Reset When the R2 Card is removed, all the CARD16 Registers except for the following Register are reset. 0b: No Register Reset Registers not reset Offset 00h (Identification and Revision Register) all bits Offset 01h (Interface Status Register) all bits Offset 02h (Power Control Register) all bits Offset 03h (Interrupt and General Control Register) D4 Offset 04h (Card Status Change Register) all bits Offset 05h (Card Status Change Interrupt Control Register) all bits Offset 16h (Additional Control Register) all bits Offset 1Eh (Global Control Register) all bits Offset 3Bh (ToPIC100 Card Timing Register) all bits Offset 3Ch (Audio / Video Switching Register) all bits Offset 3Eh (ToPIC100 Function Control Register) all bits Offset 3Fh (Toshiba Hidden Register) all bits D0: Reserved R/W possible. 8.24 Memory Window 1 Start Low Address Register |Offs|Offs|NAME |RW |D7 |D6 |D5 |D4 |D3 |D2 |D1 |D0 |PCLR| |et |et | | | | | | | | | | | | |18h |818 |PPM1S|RW |MS19|MS18|MS17|MS16|MS15|MS14|MS13|MS12|00h | D7-D0: Memory Window 1 Start Address 19-12 Set up the start address lower 8bit, which has memory access to the Card in Memory Window 1. 8.25 Memory Window 1 Start High Address Register |Offs|Offs|NAME |RW |D7 |D6 |D5 |D4 |D3 |D2 |D1 |D0 |PCLR | |et |et | | | | | | | | | | | | |19h |819 |PPM1S|RW |M1DS|M1ZW |- |- |MS23 |MS22|MS21 |MS20 |00h | D7: Data Size Set up the Data length when memory access to MEMORY WINDOW 1. 1b: 16bit Access 0b: 8bit Access D6: Zero_WS | |D6=0 |D6=1 | |8bit |Standard Cycle |0 WAIT Cycle | |MEMORY |( 6 SYS CL) |( 4 SYS CLK) | |ACCESS | | | |16bit |Set up by |0 WAIT Cycle | |MEMORY |CARD16 REG. |(2 SYS CLK) | |ACCESS |1BH- D7, D6 | | When WAIT signal is input from the Card, 0 WAIT Cycle does not occur even if D6=1. (WAIT signal from the Card is prioritized.) D5-D4: Reserved R/W possible. D3-D0: Address 20-23 Set up the start address upper 4bit, which has memory access to the Card in Memory Window 1. 8.26 Memory Window 1 Stop Low Address Register |Offs|Offs|NAME |RW |D7 |D6 |D5 |D4 |D3 |D2 |D1 |D0 |PCLR| |et |et | | | | | | | | | | | | |1Ah |81A |PPM1E|RW |ME19|ME18|ME17|ME16|ME15|ME14|ME13 |ME12 |00h | D7-D0: Memory Window 1 Stop Address 19-12 Set up the stop address lower 8bit, which has memory access to the Card in Memory Window 1. 8.27 Memory Window 1 Stop High Address Register |Offs|Offs|NAME |RW |D7 |D6 |D5 |D4 |D3 |D2 |D1 |D0 |PCLR| |et |et | | | | | | | | | | | | |1Bh |81B |PPM1E|RW |W1S1 |W1S0 |- |- |MS23|MS22 |MS21|MS20 |00h | D7-D6: Memory Window 1 16bit Memory Access Length Set up Cycle Number of 16bit Memory Access 0 0b: 3 ISA Clock 0 1b: 4 ISA Clock (1 Wait) 1 0b: 5 ISA Clock (2 Wait) 1 1b: 6 ISA Clock (3 Wait) D5-D4: Reserved R/W possible. D3-D0: Memory Window 1 Stop Address 23-20 Set up the stop address upper 4bit, which has memory access to the Card in Memory Window. 8.28 Memory Window 1 Offset Low Address Register |Offs|Offs|NAME |RW |D7 |D6 |D5 |D4 |D3 |D2 |D1 |D0 |PCLR| |et |et | | | | | | | | | | | | |1Ch |81C |PPM1O |RW |MO19|MO18|MO17|MO16|MO15|MO14|MO13 |MO12|00h | D7-D0: Memory Window 1 Offset Address 19-12 Set up the Offset Address lower 8bit, which has memory access to the Card in Memory Window 1. 8.29 Memory Window 1 Offset High Address Register |Offs|Offs|NAME |RW |D7 |D6 |D5 |D4 |D3 |D2 |D1 |D0 |PCLR| |et |et | | | | | | | | | | | | |1Dh |81D |PPM1O |RW |E1WP|E1RG|MO25|MO24|MO23|MO22|MO21 |MO20|00h | D7: Write Protect 1b: Disable 0b: Enable Memory write enabled. This bit is not affected by memory card. D6: -REG Active 1b: REG#=0 Attribute memory of the Card will be accessible. 0b: REG#=1 Common memory of the Card will be accessible. D5-D0: Address 20-25 Set up the Offset address upper 6 bit, which has memory access to the Card in Memory Window 1. 8.30 Global Control Register |Offse|Offse|NAME |RW |D7 |D6 |D5 |D4 |D3 |D2 |D1 |D0 |PCLR | |t |t | | | | | | | | | | | | |1Eh |81E |PPGCN |RW |- |- |- |- |- |RCSC |- |- |00h | D7-D3: Reserved R/W possible. D2: Card Status Change Register Initialization 1b: Initialize by Write Back This bit is reset by writing 1 to D1 [Card Status Change Register (Offset: 04H)] (Possible to reset separate bit) 0b: Initialize by Read All bits (Card Status Change Register) are reset (=0) when CARD16 REG. 04H is read, and interrupt by Card Status Change Register is canceled. (Impossible to reset separate bit.) This Register is common to Slot A and Slot B. If accessed from either, accessed to the same Register. 8.31 Memory Window 2 Start Low Address Register |Offs|Offs|NAME |RW |D7 |D6 |D5 |D4 |D3 |D2 |D1 |D0 |PCLR| |et |et | | | | | | | | | | | | |20h |820 |PPM2S|RW |MS19|MS18|MS17|MS16|MS15|MS14|MS13|MS12|00h | D7-D0: Memory Window 2 Start Address 19-12 Set up the start address lower 8bit, which has memory access to the Card in Memory Window 2. 8.32 Memory Window 2 Start High Address Register |Offs|Offs|NAME |RW |D7 |D6 |D5 |D4 |D3 |D2 |D1 |D0 |PCLR | |et |et | | | | | | | | | | | | |21h |821 |PPM2S|RW |M2DS |M2ZW |- |- |MS23|MS22|MS21 |MS20 |00h | D7: Data Size Set up data length of memory access to MEMORY WINDOW 2. 1b: 16bit access 0b: 8bit access D6: Zero_WS | |D6=0 |D6=1 | |8bit |Standard cycle |0 WAIT cycle | |MEMORY |( 6 SYS CLK) |(4 SYS CLK) | |ACCESS | | | |16bit |Set up by |0 WAIT cycle | |MEMORY |CARD16 REG. |( 2 SYS CLK) | |ACCESS |23H- D7, D6 | | When WAIT signal is input from the Card, 0 WAIT cycle does not occur even if D6=1. (WAIT signal from the Card is prioritized.) D5-D4: Reserved R/W possible. D3-D0: Address 20-23 Set up the start address upper 4bit, which has memory access to the Card in Memory Window 2. 8.33 Memory Window 2 Stop Low Address Register |Offs|Offs|NAME |RW |D7 |D6 |D5 |D4 |D3 |D2 |D1 |D0 |PCLR| |et |et | | | | | | | | | | | | |22h |822 |PPM2E|RW |ME19|ME18|ME17|ME16|ME15|ME14|ME13|ME12|00h | D7-D0: Memory Window 2 Stop Address 19-12 Set up the stop address lower 8bit, which has memory access to the Card in Memory Window 2. 8.34 Memory Window 2 Stop High Address Register |Offs|Offs|NAME |RW |D7 |D6 |D5 |D4 |D3 |D2 |D1 |D0 |PCLR | |et |et | | | | | | | | | | | | |23h |823 |PPM2E|RW |W2S1|W2S0 |- |- |MS23|MS22 |MS21|MS20 |00h | D7-D6: Memory Window 2 16bit Memory Access Length Set up the cycle number of 16bit Memory Access. 0 0b: 3 ISA Clock 0 1b: 4 ISA Clock (1 Wait) 1 0b: 5 ISA Clock (2 Wait) 1 1b: 6 ISA Clock (3 Wait) D5-D4: Reserved R/W possible. D3-D0: Memory Window 2 Stop Address 23-20 Set up the stop address upper 4bit, which has memory access to the Card in Memory Window 2. 8.35 Memory Window 2 Offset Low Address Register |Offs|Offs|NAME |RW |D7 |D6 |D5 |D4 |D3 |D2 |D1 |D0 |PCLR| |et |et | | | | | | | | | | | | |24h |824 |PPM2O |RW |MO19|MO18|MO17|MO16|MO15|MO14|MO13|MO12|00h | D7-D0: Memory Window 2 Offset Address 19-12 Set up the Offset address lower 8bit which is added to the address, which has memory access to the Card in Memory Window. 8.36 Memory Window 2 Offset High Address Register |Offs|Offs|NAME |RW |D7 |D6 |D5 |D4 |D3 |D2 |D1 |D0 |PCLR| |et |et | | | | | | | | | | | | |25h |825 |PPM2O |RW |E2WP|E2RG|MO25|MO24|MO23|MO22 |MO21 |MO20|00h | D7: Write Protect 1b: Disable 0b: Enable Memory Write enabled. This bit is not affected by memory read. D6: -REG Active 1b: REG#=0 Attribute memory of the Card will be accessible. 0b: REG#=1 Common memory of the Card will be accessible. D5-D0: Address 20-25 Set up the Offset address upper 6bit, which has memory access to the Card in Memory Window 0. 8.37 Memory Window 3 Start Low Address Register |Offs|Offs|NAME |RW |D7 |D6 |D5 |D4 |D3 |D2 |D1 |D0 |PCLR| |et |et | | | | | | | | | | | | |28h |828 |PPM3S |RW |MS19|MS18|MS17|MS16|MS15|MS14|MS13|MS12 |00h | D7-D0: Memory Window 3 Start Address 19-12 Set up the start address lower 8bit, which has memory access to the Card in Memory Window 3. 8.38 Memory Window 3 Start High Address Register |Offs|Offs|NAME |RW |D7 |D6 |D5 |D4 |D3 |D2 |D1 |D0 |PCLR | |et |et | | | | | | | | | | | | |29h |829 |PPM3S|RW |M3DS|M3ZW |- |- |MS23|MS22|MS21 |MS20 |00h | D7: Data Size 1b : 16bit access 0b : 8bit access D6: Zero_WS | |D6=0 |D6=1 | |8bit |Standard cycle |0 WAIT Cycle | |MEMORY |( 6 SYS CLK) |(4 SYS CLK) | |ACCESS | | | |16bit |Set up by |0 WAIT Cycle | |MEMORY |CARD16 REG. |(2 SYS CLK) | |ACCESS |2BH- D7, D6 | | When WAIT signal is input from the Card, 0 WAIT cycle does not occur even if D6=1. (WAIT signal from the Card is prioritized.) D5-D4: Reserved R/W possible. D3-D0: Address 20-23 Set up the start address upper 4bit, which has memory access to the Card in Memory Window 3. 8.39 Memory Window 3 Stop Low Address Register |Offs|Offse|NAME |RW |D7 |D6 |D5 |D4 |D3 |D2 |D1 |D0 |PCLR| |et |t | | | | | | | | | | | | |2Ah |82A |PPM3E|RW |ME19|ME18|ME17|ME16|ME15|ME14|ME13|ME12|00h | D7-D0: Memory Window 3 Stop Address 19-12 Set up the stop address lower 8bit, which has memory access to the Card in Memory Window 3. 8.40 Memory Window 3 Stop High Address Register |Offse|Offs|NAME |RW |D7 |D6 |D5 |D4 |D3 |D2 |D1 |D0 |PCLR | |t |et | | | | | | | | | | | | |2Bh |82B |PPM3E |RW |W3S1 |W3S0 |- |- |MS23|MS22|MS21|MS20 |00h | D7-D6: Memory Window 3 16bit Memory Access Length Set up the Cycle Number of 16bit Memory Access 00b: 3 ISA Clock 01b: 4 ISA Clock (1 Wait) 10b: 5 ISA Clock (2 Wait) 11b: 6 ISA Clock (3 Wait) D5-D4: Reserved R/W possible. D3-D0: Memory Window 3 Stop Address 23-20 Set up the stop address upper 4bit, which has memory access to the Card in Memory Window 3. 8.41 Memory Window 3 Offset Low Address Register |Offs|Offse|NAME |RW |D7 |D6 |D5 |D4 |D3 |D2 |D1 |D0 |PCLR| |et |t | | | | | | | | | | | | |2Ch |82C |PPM3O |RW |MO19|MO18|MO17|MO16|MO15|MO14|MO13|MO12|00h | D7-D0: Memory Window 3 Offset Address 19-12 Set up the Offset address lower 8bit which is added to the address, which has memory access to the Card in Memory Window 3. 8.42 Memory Window 3 Offset High Address Register |Offs|Offs|NAME |RW |D7 |D6 |D5 |D4 |D3 |D2 |D1 |D0 |PCLR| |et |et | | | | | | | | | | | | |2Dh |82D |PPM3O |RW |E3WP|E3RG|MO25|MO24|MO23|MO22|MO21|MO20|00h | D7: Write Protect 1b: Disable 0b: Enable Memory write enabled. This bit is not affected by memory read. D6: -REG Active 1b: REG#=0 Attribute memory of the Card will be accessible. 0b: REG#=1 Common memory of the Card will be accessible. D5-D0: Address 20-25 Set up the Offset address upper 6bit, which has memory access to the Card in Memory Window 0. 8.43 Memory Window 4 Start Low Address Register |Offs|Offs|NAME |RW |D7 |D6 |D5 |D4 |D3 |D2 |D1 |D0 |PCLR | |et |et | | | | | | | | | | | | |30h |830 |PPM4S|RW |MS19|MS18|MS17|MS16|MS15|MS14|MS13|MS12|00h | D7-D0b: Memory Window 4 Start Address 19-12 Set up the start address lower 8bit, which has memory access to the Card in Memory Window 4. 8.44 Memory Window 4 Start High Address Register |Offs|Offs|NAME |RW |D7 |D6 |D5 |D4 |D3 |D2 |D1 |D0 |PCLR | |et |et | | | | | | | | | | | | |31h |831 |PPM4S |RW |M4DS|M4ZW |- |- |MS23|MS22|MS21|MS20 |00h | D7: Data Size 1b : 16bit Access 0b : 8bit Access D6: Zero_WS | |D6=0 |D6=1 | |8bit |Standard Cycle |0 WAIT Cycle | |MEMORY |(6 SYS CLK) |(4 SYS CLK) | |ACCESS | | | |16bit |Set up by |0 WAITCycle | |MEMORY |CARD16 REG. |( 2 SYS CLK) | |ACCESS |33H- D7, D6 | | When WAIT signal is input from the Card, 0 WAIT cycle does not occur even if D6=1. (WAIT signal from the Card is prioritized.) D5-D4: Reserved R/W possible. D3-D0: Address 20-23 Set up the start address upper 4bit, which has memory access to the Card in Memory Window 4. 8.45 Memory Window 4 Stop Low Address Register |Offs|Offse|NAME |RW |D7 |D6 |D5 |D4 |D3 |D2 |D1 |D0 |PCLR| |et |t | | | | | | | | | | | | |32h |832 |PPM4E |RW |ME19|ME18|ME17|ME16|ME15|ME14|ME13|ME12|00h | D7-D0: Memory Window 4 Stop Address 19-12 Set up the stop address lower 8bit, which has memory access to the Card in Memory Window 4. 8.46 Memory Window 4 Stop High Address Register |Offs|Offse|NAME |RW |D7 |D6 |D5 |D4 |D3 |D2 |D1 |D0 |PCLR | |et |t | | | | | | | | | | | | |33h |833 |PPM4E|RW |W4S1|W4S0|- |- |MS23 |MS22|MS21 |MS20 |00h | D7-D6: Memory Window 4 16bit Memory Access Length Set up the cycle number of 16bit Memory Access 0 0b: 3ISA Clock 0 1b: 4ISA Clock (1 Wait) 1 0b: 5ISA Clock (2 Wait) 1 1b: 6ISA Clock (3 Wait) D5-D4: Reserved R/W possible D3-D0: Memory Window 4 Stop Address 23-20 Set up the stop address upper 4bit which has memory access to the Card in Memory Window 4. 8.47 Memory Window 4 Offset Low Address Register |Offs|Offs|NAME |RW |D7 |D6 |D5 |D4 |D3 |D2 |D1 |D0 |PCLR| |et |et | | | | | | | | | | | | |34h |834 |PPM4O |RW |MO19|MO18|MO17|MO16|MO15 |MO14|MO13|MO12|00h | D7-D0: Memory Window 4 Offset Address 19-12 Set up the Offset address lower 8bit which is added to the address, which has memory access to the Card in Memory Window 4. 8.48 Memory Window 4 Offset High Address Register |Offs|Offs|NAME |RW |D7 |D6 |D5 |D4 |D3 |D2 |D1 |D0 |PCLR| |et |et | | | | | | | | | | | | |35h |835 |PPM4O |RW |E4WP|E4RG|MO25|MO24|MO23|MO22|MO21|MO20|00h | D7: Write Protect 1b: Disable 0b: Enable Memory write enabled. This bit is not affected by memory read. D6: -REG Active 1b: REG#=0 Attribute memory of the Card will be accessible. 0b: REG#=1 Common memory of the Card will be accessible. D5-D0: Address 20-25 Set up the Offset address upper 6bit, which has memory access to the Card in Memory Window 0. 49. ToPIC100 Card Timing Register Write is enabled when SlotControl Register - D_LOCK ( Config. A0H-D5 ) =0. Write is diabled when the bit is set to 1. (WRITE PROTECT) When ToPIC100 Function Control Register - Card Timing Enable (Card16. 3Eh-D3)= 1, this Register settings to the access timing of Card16 are valid, and read of the Register value is enabled. When Card Timing Enable = 0, the Register settings are invalid, and 0 is always read. (READ ENABLE) |Offs|Offs|NAME |RW |D7 |D6 |D5 |D4 |D3 |D2 |D1 |D0 |PCLR | |et |et | | | | | | | | | | | | |3Bh |83B |PPCTM |RW |INP#|- |SCY1|SCY0|HCY3|HCY2|HCY1 |HCY0 |00h | D7: INPACK# In case of READ ENABLE, possible to read the status of INPACK# signal of the slot IF. D6: Reserved R/W possible. D5-D4: Setup Cycle Set up Wait number inserted to Set Up Cycle of Card Access in case of READ ENABLE. D5 D4 WAIT CYCLE 0 0 Non 0 1 1PCICLK 1 0 2PCICLK 1 1 3PCICLK D3-D0: Hold Cycle Set up Wait Number inserted to Hold Cycle of Card Access in case of READ ENABLE. Wait Cycle is not inserted when READ DIABLE. D3 D2 D1 D0 WAITCYCLE 0 0 0 0 Non 0 0 0 1 1PCICLK . . 1 1 1 1 15PCICLK 8.50 Audio/Video Switching Register |Offse|Offse|NAME |RW |D7 |D6 |D5 |D4 |D3 |D2 |D1 |D0 |PCLR | |t |t | | | | | | | | | | | | |3Ch |83C |PPAVS |RW |- |- |- |- |- |- |ACNT |VCNT |00h | D7-D2: Reserved R/W possible. D1: AUDIO Control 1b : ZV - AUDIO ENABLE 0b : ZV - AUDIO DISABLE (SPKER#, INPACK# is HI fixed.) This bit is changed working with CONFIG. 9CH-D0. D0: VIDEO Control 1b : ZV - VIDEO ENABLE 0b : ZV - VIDEO DISABLE This bit is changed working with CONFIG. 9CH-D0. ( D1 - D0 can read the status of ZV Bus when ZV Configuration Register (AEh) D1, ZV mode select bit of Configuration Register is set to 1. 1b: ZV Bus is running. 0b: ZV Bus is no in use. When ZV mode select bit is set to 0, the value written in ZV Control Register can be read. D1 - D0 bit works with ZV Control Register (9Ch) bit0 of Configuration Register mutually, and the value of this Register will be changed when 9Ch bit0 has a change. Audio / Video have the 9Ch bit0 in common, and both D1 and D0 will be set to 1 if the bit is set to 1. 51. ToPIC100 Function Control Register Write is enabled when bit5 (ID_LOCK) of Slot Control Register (Config. offset : A0h) is set to 0. Write is disabled when the bit is set to 1. When ID_LOCK = 1, 0 is read even if the Register has a value set in it. When ID_LOCk = 0, the value in the Register is read. |Offs|Offse|NAME |RW |D7 |D6 |D5 |D4 |D3 |D2 |D1 |D0 |PCLR | |et |t | | | | | | | | | | | | |3Eh |83E |PPTFN |RW |- |PCBE |- |- |CTE |- |VSSE |CPE|00h | D7: Reserved R/W possible. D6: Power Control Buffer Enable 1b : SLOT Power Supply (P-SW) control signal OFF ( Hi-Z) RIOUT = 0 in case of BUFFER OFF (SUSPEND) 0b : Disable D5-D4: Reserved R/W possible. D3: Card Timing Enable 1b: Enable Card Access Timing is determined by the set in ToPIC100 Card Timing Register (Card16. 3Bh). 0b: Disable Value in Card16. 3Bh is invalid. D2: Reserved R/W possible. D1: Voltage Sense Status Enable 1b : Read Additional General Control Register (Card16. 16H) - D7, D6, and the VS1, VS2 pin status can be monitored. 0b : Only the value in the Register can be read when reading Additional General Control Register (16H). D0: Card Power Enable 1b : 3V Card support Enabled 0b : 3V Card support Disabled This bit changes Card Power Supply that is set in Card16 Reg.02H. 9 CardBus Register 9.1 Socket Event Register This Register is used to verify the interrupt occurred by status change. Card service reads Socket Present State Register (CB REG 008H) and this Register to determine the cause of interrupt. Card service must clear the field in which the interrupt is processed after the interrupt is completed. This Register is cleared on the following conditions. 1) Resume when CardBus Socket Registers Control Reg. - Resume Reset Enable bit (Config.Reg.:A4h - D31)=1b 2) Card removed when Config.Reg.A4H - D30 "CardBus Card Removal Reset Enable bit"=1b 3) Reset of PCI Bus. 4) Assert of CRST#. Lower 4bit (D3 - D0) is reset by writing 1b. This Register becomes invalid when Software Card Detect is selected in Detect Method Select bit =1b of Card Detect Control Register (Config.Reg. A3h). |Offset| |NAME |RW |D31 | | |D4 |D3 |D2 |D1 |D0 |PCLR| |000h | |PPSKE |R |- | | | |PWCY |CCD2 |CCD1 |WKUP |00h | D3: PowerCycle Indicate D3 (Socket Present State Register (CB Reg. 008H)) will change or not. 1b: Changed 0b: Not changed D2: CCD2# Indicate D2 (Socket Present State Register (CB Reg. 008H)) will change or not. 1b: Changed 0b: Not changed D1: CCD1# Indicate D1 (Socket Present State Register (CB Reg. 008H)) will change or not. 1b: Changed 0b: Not changed D0: CSTSCHG/WAKEUP Indicate D0 (Socket Present State Register (CB Reg. 008H)) will change or not. 1b: Changed 0b: Not changed 9.2 Socket Mask Register This register provides a card service with the function for controlling Status Change interrupt case. It masks the interrupt to Status Change interrupt cause set in Event Register. This Register is reset at the time of resume when Resume Reset Enable bit of CardBus Socket Registers Control Register (Config. offset:A4h) is set to 1. Also, it is reset when the card is removed (CardBus Card Removal Reset Enable bit of CardBus Socket Registers Control Register (Config. offset:A4h) is set to 1), PCI Bus is reset, and CRST# is asserted. |Offset| |NAME |RW |D31 | | |D4 |D3 |D2 |D1 |D0 |PCLR | |004h | |PPSKM |RW |- | | | |MPWC |MCD2 |MCD1 |MWKU |00h | D3: PowerCycle Mask This bit controls Status Change Interrupt when Socket Event Register - Power Cycle (CB Reg.000H-D3) is set to 1. 0b: Enable (Default) 1b: Disable D2-D1: CCD2#, CCD1# Mask 0 0b: Status Change Interrupt by Card Detect is masked. (Default) 0 1b: Canceled ( Status Change Interrupt by Card Detect is masked.) 1 0b: Canceled ( Status Change Interrupt by Card Detect is masked.) 1 1b: Status Change Interrupt by Card Detect is not masked. D0: CSTSCHG/WAKEUP Mask This bit controls Status Change Interrupt when Socket Event Register - CSTSCHG / WAKEUP (CB Reg.000H-D0) is set to 1. 0b: Enable 1b: Disable 9.3 Socket Present State Register This Register is read-only indicating status of socket. Some bits are directly set by the socket signal and the others are set according to the change of socket status. This Register is reset at the time of resume when Resume Reset Enable bit in CardBus Socket Registers Control Register (Config. offset : A4h) is set to 1, card removal when CardBus Card Removal Reset Enable bit in CardBus Socket Registers Control Register (Config. offset : A4h) is set to 1, or reset of PCI Bus. |Confi| |NAME |RW|D31 |D30 |D29 |D28 |D27 | | |D16 |PCLR | |g | | | | | | | | | | | | | |008h | |PPSPS|R |- |- |- |- |- | | | |3000h| | | | | |D15 |D14 |D13 |D12 |D11 |D10 |D9 |D8 |PCLR | | | | | |- |- |CDYV |CDXY |CD3V |CD5V |BADV |DLOS|00h | | | | | |D7 |D6 |D5 |D4 |D3 |D2 |D1 |D0 |PCLR | | | | | |NCAD |CINT|CARD |PC16 |PWCY |CCD2 |CCD1 |STCH|00h | D31: YVsocket "0" fixed. Indicate if support for Y.YV Card is possible. This controller supports only 5V Card and 3.3V Card. D30: XVsocket "0" fixed. Indicate if support for X.XV Card is possible. This controller supports only 5V Card and 3.3V Card. D29: 3Vsocket "1" fixed. This controller supports 3.3V Card. D28: 5Vsocket "1" fixed. This controller supports 5V Card. D27-14: Reserved "0" fixed. D13: YVcard 1b: Card detected has Y.YV function. 0b: Card detected does not have Y.YV function. D12: XVcard 1b: Card detected has X.XV function. 0b: Card detected does not have X.XV function. D11: 3Vcard 1b: Card detected has 3V function. 0b: Card detected does not have 3V function. D10: 5Vcard 1b: Card detected has 5V function. 0b: Card detected does not have 5V function. D9: BadVCCReq This bit is set to 1b when the voltage supplied to the socket set by Card Service indicates beyond the limit detected by CVS<2:1>,CCD<2:1># pin. D8: DataLost 1b: Data disappeared Indicate the data might have disappeared when the Card was removed. This bit is set by the following factors. 1) Transaction ended abnormal. 2) Data was remained at the buffer of Socket when the Card was removed. This bit must be reset by Card Service when Removal Event Status Change Interrupt processing. 0b: Data normal D7: NotACard 1b: Card inserted is not supported by this controller. This bit is not changed until it recognizes R2 Card or CardBus Card. ( i.e. It is set only when Card is inserted.) 0b: No Card inserted that this controller does not support. D6: Card Interrupt 1b: Interrupt signal from the Card (IREQ#, CINT#) occurred. 0b: Interrupt signal not occur. D5: CBcard 1b: CardBus Card is inserted. 0b: CardBus Card is not inserted. D4: 16card 1b: R2 Card is inserted. 0b: R2 Card is not inserted. D3: PowerCycle 1b: Card Power Supply stable. 0b: Card Power Supply unstable. This bit can not be set when Card Detect Block is ON. D2: CCD2# Indicate CCD2# status on IF. This bit can not be updated when Card Detect Block is ON. 1b: CCD2# is High. (Card not inserted.) 0b: CCD2# is Low. (Card inserted.) D1: CCD1# Indicate CCD1# status on IF. This bit can not be updated when Card Detect Block is ON. 1b: CCD1# is High. (Card not inserted.) 0b: CCD1# is Low. (Card inserted.) D0: CSTSCHG Indicate CSTSCHG status. This bit can not be updated when Card Detect Block is ON. This bit is cleared when CRST# is asserted. 1b: CSTSCHG is High (assert) 0b: CSTSCHG is Low 9.4 Socket Force Register This Register is for Debug, and is able to change the value in Socket Event Register and Socket Present State Register by force. However, this Register does not exist physically. It is able to reflect data to Socket Present State Register and Socket Event Register by writing to this Register. |Config| |NAME |RW |D31 | | | | | | |D16 |PCLR | |00Ch | |PPSKF|RW |- | | | | | | | |0000h | | | | | |D15 |D14 |D13 |D12 |D11 |D10 |D9 |D8 |PCLR | | | | | |- |CVST |CDYV |CDXY |CD3V |CD5V |BADV |DLOS |00h | | | | | |D7 |D6 |D5 |D4 |D3 |D2 |D1 |D0 |PCLR | | | | | |NCAD |CINT |CARD |PC16 |PWCY |CCD2 |CCD1 |STCH |00h | D14: CVStest When 1b is written, detect CVS<2:1>, CCD<2:1># status and change field of nVcard in Socket Present State Register. This field is used for reset the nVcard field when the field is changed by force. D13: YVcard Write data is written to YVcard field in Socket Present State Register, and Power Control Register (CB REG. 010H) is reset by writing to this bit. Since parity voltage of the Card is changed, 1b has to be set to CVStest in Socket Force Register, and YVcard field in Socket Present State Register has to be reset before setting Power Control Register to make power supply for the Socket. D12: XVcard Write data is written to XVcard field in Socket Present State Register, and Power Control Register (CB REG. 010H) is reset by writing to this bit. Since parity voltage of the Card is changed, 1b has to be set to CVStest in Socket Force Register, and YVcard field in Socket Present State Register has to be reset before setting Power Control Register to make power supply for the Socket. D11: 3Vcard Write data is written to 3Vcard field in Socket Present State Register by writing to this bit. Power Control Register is reset when the data written to this bit is different from 3Vcard field. Since parity voltage of the Card is changed, 1b has to be set to CVStest in Socket Force Register, and nVcard field in Socket Present State Register has to be reset before setting Power Control Register to make power supply for the Socket. D10: 5Vcard Write date is written to 5Vcard in Socket Present State Register by writing to this bit. Power Control Register is reset when the data written to this bit is different from 5Vcard field. Since parity voltage of the Card is changed, 1b has to be set to CVStest in Socket Force Register, and nVcard field in Socket Present State Register has to be reset before setting Power Control Register to make power supply for the Socket. D9: BadVCCReq Write date is written to BadVCCReq field in Socket Present State Registerby writing to this bit. D8: DataLost Write data is written to DataLost field in Socket Present State Register by writing to this bit. D7: NotACard Write data is written to NotACard field in Socket Present State Register by writing to this bit. If the Card is in Socket (CCD1, CCD2 assert), write is invalid. D6: CardBus Interrupt Enable Set up to D6 in Socket Present State Register. D5: CBcard Write data is written to CBcard field in Socket Present State Register by writing to this bit. If the Card is in Socket (CCD1, CCD2 assert), write is invalid. D4: 16card Write data is written to 16card field in Socket Present State Register by writing to this bit. If the Card is in Socket (CCD1, CCD2 assert), write is invalid. D3: PowerCycle Power Cycle bit in Socket Event Register is set by writing 1b to this bit. However, Power Cycle bit in Socket Present State Register has no change, and IF power supply continues to reflect on Socket Present State Register. D2: CCD2# CCD2# bit in Socket Event Register is set by writing 1b to this bit. However, CCD2# bit in Socket Present State Register has no change, and CCD2# pin continues to reflect on Socket Present State. Writing 0b makes no change. D1: CCD1# CCD1# bit in Socket Event Register is set by writing 1b to this bit. However, CCD1# bit in Socket Present State Register has no change, and CCD1# pin continues to reflect on Socket Present State. Writing 0b makes no change. D0: CSTSCHG CSTSCHG bit in Socket Event Register is set by writing 1b to this bit. However, CSTSCHG bit in Socket Present State Register has no change, and CSTSCHG pin continues to reflect on Socket Present State. Writing 0b makes no change. 9.5 Power Control Register This Register controls VPP and VCC Power Supplied to the Socket. This Register is reset by the following conditions. 1) PCIRST# is active. 2) nVcard field in Socket Force Register (CB Reg.00CH) is changed by force. 3) Resume when CardBus Socket Registers Control Register - Resume Reset Enable bit (Config. offset : A4H-D31)=1b 4) Card is removed when CardBus Socket Registers Control Register - CardBus Card Removal Reset Enable bit(Config. offset : A4h- D30)=1b |Offset| |NAME |RW |D31 | | | | | | |D8 |PCLR | |010h | |PPPWC |RW |- | | | | | | | |00h | | | | | |D7 |D6 |D5 |D4 |D3 |D2 |D1 |D0 |PCLR | | | | | |CKRN|VCC2 |VCC1|VCC0 |- |VPP2 |VPP1 |VPP0 |00h | D7: StopClock bit This bit controls Enable/Disable for CLKRUN# protocol in between NOVA - Card. 1b : Enable 0b : Disable (Default) D6-D4: VCC Control bit 000b : Power off (Default ) 001b : Reserved 010b : 5.0V 011b : 3.3V 1xxb : Reserved D2-D0: VPP Control bit 000b : Power off (Default) 001b : 12.0V 010b : 5.0V 0 11b : 3.3V 1 x x b : Reserved ----------------------- TOSHIBA CORPORATION No. 5MD3198A0001 [pic] ----------------------- ToPIC100 Specification (2) TOSHIBA CONFIDENTIAL