Caching is controlled completely by the CPU, transparent of the programmer.Only in some designs. Architectures like MIPS allow for both a cache-coherent or non-cache-coherent design. In a non-cache-coherent design, the cache is not transparent, and the kernel programmer is responsible for cache management; marking pages as dirty, flushing cache, etc. These designs are significantly more difficult to program and are present on some SGI machines, making porting to those machines a significant task.
Theoretically, higher performance can be achieved in a non-cache-coherent design, since the programmer would ostensibly know more about which data is most frequently used on his system and be able to customize his kernel for that. Also, it requires less glue logic on the board. However, the intent may be thwarted if the programmer doesn't have all the documentation (or skills) necessary to make efficient use of a software controlled cache.