|TOSHIBA PCI to PC-Card16/CardBus Controller | |ToPIC100 | |Specification (2): | |Register | |Draft( Rev. 01.4 ) 1998-10-07 | Contents 6 Internal Registe.............................................5 6.1 Register ................................... ......................5 6.1.1PC-Card Configuration MAP ..5 6.1.2PC-Card 16 Register 6 6.1.3PC-Card 16 Register - continued 7 6.1.4CardBus Register 7 7 ToPIC100 Configuration Register 8 7.1 Vendor ID Register 8 7.2 Device ID Register 8 7.3 Command Register 9 7.4 Status Register 11 7.5 Revision ID Register 13 7.6 Class Code Register 13 7.7 Header Type Register 13 7.8 Base Address Register 13 7.9 Capability Pointer Register 15 7.10 Secondary Status Register 15 7.11 PCI Bus Number Register 17 7.12 Secondary Bus Number Register 17 7.13 Subordinate Bus Number Register 17 7.14 1st Memory window Base Register 18 7.15 1st Memory window Limit Register 18 7.16 2nd Memory window Base Register 19 7.17 2nd Memory window Limit Register 19 7.18 1st I/O window Base(Lower) Register 20 7.19 1st I/O window Base(Upper) Register 20 7.20 1st I/O window Limit(Lower) Register 20 7.21 1st I/O window Limit(Upper) Register 20 7.22 2nd I/O window Base(Lower) Register 21 7.23 2nd I/O window Base(Upper) Register 21 7.24 2nd I/O window Limit(Lower) Register 21 7.25 2ndI/O window Limit(Upper) Register 21 7.26 Interrupt Line Register 22 7.27 Interrupt Pin Register 22 7.28 Bridge Control Register 23 7.29 Subsystem Vendor ID Register 26 7.30 Subsystem Device ID Register 26 7.31 PC Card16 Legacy Mode Base Address Register 26 7.32 Capability ID Register 27 7.33 Next Item Ptr Register 27 7.34 Power Management Capabilities (PMC) Register 28 7.35 Power Management Control/Status (PMCSR) Register 29 7.36 PMCSR PCI to CardBus Bridge Support Extensions Register 30 7.37 Data Register 30 7.38 CardBus Socket Power Detect Control Register 31 7.39 ZV Control Register 32 7.40 Slot Control Register 33 7.41 Interrupt Control Register 34 7.42 Card Detect Control Register 35 7.43 CardBus Socket Register Control Register 36 7.44 Wake Up Control Register 38 7.45 Serial Interrupt Control Register 40 7.46 MISC1 Register 41 7.47 ZV Configuration Register 42 7.48 BUFFER CONTROL Register 43 7.49 Debug Register 44 7.50 Serial Power Control Register 46 7.51 IRQ Routing Register 47 7.52 Additional Control Register 49 7.53 Configuration Control Register 50 8 PC-Card16 Register 53 8.1 Identification and Revision Register 53 8.2 Interface Status Register 54 8.3 Power Control Register 55 8.4 Interrupt and General Control Register 58 8.5 Card Status Change Register 59 8.6 Card Status Change Interrupt Control Register 61 8.7 Window Enable Register 63 8.8 I/O Window Control Register 65 8.9 I/O Window 0 Start Low Address Register 67 8.10 I/O Window 0 Start High Address Register 67 8.11 I/O Window 0 Stop Low Address Register 67 8.12 I/O Window 0 Stop High Address Register 67 8.13 I/O Window 1 Start Low Address Register 68 8.14 I/O Window 1 Start High Address Register 68 8.15 I/O Window 1 Stop Low Address Register 68 8.16 I/O Window 1 Stop High Address Register 68 8.17 Memory Window 0 Start Low Address Register 69 8.18 Memory Window 0 Start High Address Register 69 8.19 Memory Window 0 Stop Low Address Register 70 8.20 Memory Window 0 Stop High Address Register 70 8.21 Memory Window 0 Offset Low Address Register 71 8.22 Memory Window 0 Offset High Address Register 71 8.23 Additional General Control Register 72 8.24 Memory Window 1 Start Low Address Register 74 8.25 Memory Window 1 Start High Address Register 74 8.26 Memory Window 1 Stop Low Address Register 75 8.27 Memory Window 1 Stop High Address Register 75 8.28 Memory Window 1 Offset Low Address Register 76 8.29 Memory Window 1 Offset High Address Register 76 8.30 Global Control Register 77 8.31 Memory Window 2 Start Low Address Register 78 8.32 Memory Window 2 Start High Address Register 78 8.33 Memory Window 2 Stop Low Address Register 79 8.34 Memory Window 2 Stop High Address Register 79 8.35 Memory Window 2 Offset Low Address Register 80 8.36 Memory Window 2 Offset High Address Register 80 8.37 Memory Window 3 Start Low Address Register 81 8.38 Memory Window 3 Start High Address Register 81 8.39 Memory Window 3 Stop Low Address Register 82 8.40 Memory Window 3 Stop High Address Register 82 8.41 Memory Window 3 Offset Low Address Register 83 8.42 Memory Window 3 Offset High Address Register 83 8.43 Memory Window 4 Start Low Address Register 84 8.44 Memory Window 4 Start High Address Register 84 8.45 Memory Window 4 Stop Low Address Register 85 8.46 Memory Window 4 Stop High Address Register 85 8.47 Memory Window 4 Offset Low Address Register 86 8.48 Memory Window 4 Offset High Address Register 86 8.49 ToPIC100 Card Timing Register 87 8.50 Audio/Video Switching Register 88 8.51 ToPIC100 Function Control Register 89 9 CardBus Register 90 9.1 Socket Event Register 90 9.2 Socket Mask Register 91 9.3 Socket Present State Register 92 9.4 Socket Force Register 95 9.5 Power Control Register 98 Internal Register 1 Register 1 PC-Card Configuration MAP |31 |23 |15 |07 |00 |Port | |Device ID(0617h) |Vendor ID(1179h) | 00h | |Status(0490h) |Command(0000h) | 04h | |Class Code(060700h) |Revision | 08h | | |ID(00h) | | | |Header | | | 0Ch | | |Type(82h) | | | | |Base Address | 10h | |Secondary Status | Latency |Capability | 14h | | |Timer |Pointer | | | |Subordinate Bus|Secondary Bus |PCI Bus Number | 18h | | | |Number | | | | |Number | | | | |1st Memory window Base | 1Ch | |1st Memory window Limit | 20h | |2nd Memory window Base | 24h | |2nd Memory window Limit | 28h | |1st I/O window Base (Upper) |1st I/O window Base (Lower) | 2Ch | |1st I/O window Limit (Upper) |1st I/O window Limit (Lower) | 30h | |2nd I/O window Base (Upper) |2nd I/O window Base (Lower) | 34h | |2nd I/O window Limit (Upper) |2nd I/O window Limit (Lower) | 38h | |Bridge Control |Interrupt Pin |Interrupt Line | 3Ch | |Subsystem Device ID(0000h) |Subsystem Vendor ID(0000h) | 40h | |PC Card16 Legacy Mode Base Address | 44h | | | | | |48h-7F| | | | | |h | |Power Management Capabilities |Next Item Ptr |Capability ID | 80h | |(PMC) | | | | |Data |PMCSR PCI to |Power Management Control/Status | 84h | | |CardBus Bridge |(PMCSR) | | | |Support | | | | | | | | 88h | |TOSHIBA RESERVED | 8Ch | | |90h | |CardBus Socket Power Detect Control | | | | | | |94h-9B| | | | | |h | | | | |ZV Control | 9Ch | |Card Detect | |Interrupt |Slot Control | A0h | |Control | |Control | | | |CardBus Socket Register Control | A4h | |Wake Up Control | A8h | |Internal PCI |ZV |MISC1 |Serial | ACh | |Retry |Configuration | |Interrupt | | | | | |Control | | |TOSHIBA RESERVED | | | | B0h | |TOSHIBA RESERVED | | | | B4h | |Debug |TOSHIBA RESERVED | | | B8h | | |Serial Power |TOSHIBA RESERVED | BCh | | |Control | | | |IRQ Routing | C0h | | | | |Additional | C4h | | | | |Control | | | | | | |C8-FBh| |Configuration Control | FCh | 6.1.2 PC-Card 16 Register (1)Base Address :Slot Control Register (A0h/Device ID:0617h) (2)Base Address :Base Address(10h/Device ID:0617h) |Offset(1|Offset(2|Register | |R/W |CLR | |) |) | | | | | |- |N/A |Port 3E Index |PP3EI7-0 |RW |P | |00h |800 |Identification and Revision |PPRVN7-0 |RW |P | |01h |801 |Interface Status |PPIFS7-0 |R |- | |02h |802 |Power Control |PPPCN7-0 |RW |P | |03h |803 |Interrupt and General Control |PPICN7-0 |RW |P | |04h |804 | |PPCSC7-0 |RW |P | |05h |805 |Card Status Change |PPCSI7-0 |RW |P | |06h |806 |Card Status Change Interrupt |PPWEN7-0 |RW |P | |07h |807 |Control |PPWCN7-0 |RW |P | |08h |808 |Window Enable |PPI0S7-0 |RW |P | |09h |809 |I/O Window Control |PPI0S15-8 |RW |P | |0Ah |80A | |PPI0E7-0 |RW |P | |0Bh |80B |I/O Window 0 Start Low Address |PPI0E15-8 |RW |P | |0Ch |80C | |PPI1S7-0 |RW |P | |0Dh |80D |I/O Window 0 Start High Address |PPI1S15-8 |RW |P | |0Eh |80E |I/O Window 0 Stop Low Address |PPI1E7-0 |RW |P | |0Fh |80F | |PPI1E15-8 |RW |P | |10h |810 |I/O Window 0 Stop High Address |PPM0S7-0 |RW |P | |11h |811 | |PPM0S15-8 |RW |P | |12h |812 |I/O Window 1 Start Low Address |PPM0E7-0 |RW |P | |13h |813 | |PPM0E15-8 |RW |P | |14h |814 |I/O Window 1 Start High Address |PPM0O7-0 |RW |P | |15h |815 | |PPM0O15-8 |RW |P | |16h |816 |I/O Window 1 Stop Low Address |PPACN7-0 |RW |P | |18h |818 | |PPM1S7-0 |RW |P | |19h |819 |I/O Window 1 Stop High Address |PPM1S15-8 |RW |P | |1Ah |81A | |PPM1E7-0 |RW |P | |1Bh |81B |Memory Window 0 Start Low Address |PPM1E15-8 |RW |P | |1Ch |81C | |PPM1O7-0 |RW |P | |1Dh |81D |Memory Window 0 Start High Address|PPM1O15-8 |RW |P | |1Eh |81E | |PPGCN7-0 |RW |P | |20h |820 |Memory Window 0 Stop Low Address |PPM2S7-0 |RW |P | |21h |821 |Memory Window 0 Stop High Address |PPM2S15-8 |RW |P | |22h |822 | |PPM2E7-0 |RW |P | |23h |823 |Memory Window 0 Offset Low Address|PPM2E15-8 |RW |P | |24h |824 | |PPM2O7-0 |RW |P | |25h |825 |Memory Window 0 Offset High |PPM2O15-8 |RW |P | |28h |828 |Address |PPM3S7-0 |RW |P | |29h |829 |Additional General Control |PPM3S15-8 |RW |P | |2Ah |82A | |PPM3E7-0 |RW |P | |2Bh |82B |Memory Window 1 Start Low Address |PPM3E15-8 |RW |P | |2Ch |82C |Memory Window 1 Start High Address|PPM3O7-0 |RW |P | |2Dh |82D | |PPM3O15-8 |RW |P | |30h |830 |Memory Window 1 Stop Low Address |PPM4S7-0 |RW |P | |31h |831 | |PPM4S15-8 |RW |P | |32h |832 |Memory Window 1 Stop High Address |PPM4E7-0 |RW |P | |33h |833 | |PPM4E15-8 |RW |P | | | |Memory Window 1 Offset Low Address| | | | | | | | | | | | | |Memory Window 1 Offset High | | | | | | |Address | | | | | | |Global Control | | | | | | |Memory Window 2 Start Low Address | | | | | | | | | | | | | |Memory Window 2 Start High Address| | | | | | | | | | | | | |Memory Window 2 Stop Low Address | | | | | | | | | | | | | |Memory Window 2 Stop High Address | | | | | | | | | | | | | |Memory Window 2 Offset Low Address| | | | | | | | | | | | | |Memory Window 2 Offset High | | | | | | |Address | | | | | | |Memory Window 3 Start Low Address | | | | | | |Memory Window 3 Start High Address| | | | | | | | | | | | | |Memory Window 3 Stop Low Address | | | | | | |Memory Window 3 Stop High Address | | | | | | |Memory Window 3 Offset Low Address| | | | | | |