Some tidbits about the Intel Pentium (P5) processor:
– It introduced MSR (Model Specific Registers)
– It introduced TSC (Time Stamp Counter)
– It has two pipelines (thus is superscalar) but executes instructions in-order, so code must be specifically optimized for the P5 pipeline for optimally-performing instruction scheduling
– It has a local APIC (Advanced Programmable Interrupt Controller), but the local APIC is disabled by a CPU pin rather than by software as in P6 and later CPUs (so Linux cannot enable it); the APIC is usually enabled on SMP Pentium boards
– It has Machine Check Exception, but many motherboards have a design flaw that causes false events, so the user must enable it with the 'mce' Linux boot parameter
– It has two significant bugs (FDIV and F00F)
– It introduced split core/IO voltage
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