System design hazards

There are several hazards you want to avoid if your system can have its power removed at any point.

– Writing to an EEPROM. If this is to be done, the user should be warned that power removal will corrupt the EEPROM. If this is to be done by firmware (as in IBM Thinkpads and their security serial EEPROM), there should always be a backup EEPROM that can be used in the case that power is removed during the write.

– Hardware that requires several discrete I/O cycles to complete a write to a non-volatile (preserved across boot, and perhaps required by system firmware) region. For example, the PC RTC (Real Time Clock) is notorious for becoming corrupted when a NMI or SMI arrives at the wrong moment due to its index/data register pair design. The 8042 NMI mask bit is there for a reason; use it. The SMM infrastructure allows for restarting I/O instructions, but it does not know anything about the RTC. Therefore, the SMI handler must scan the region around EIP to ensure that the SMI didn't arrive between a write to port 0x70 and a read from port 0x71.

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