P6 is a RISC

["Robert George" <george@holmes.cs.nps.navy.mil>]

On February 16, Intel presented the details of the P6 architecture at the
International Solid-State Cicuits Conference.  Intel has abandoned the idea of
trying to execute the complex x86 instruction set directly. Instead, the P6
chip translates the CISC instructions on the fly to RISC instructions, dubbed
micro-operations or "uops".

Intel has published the paper from the proceedings of ISSCC on the web at:

http://web.jf.intel.com:80/procs/p6/index.html

Robert

-- 
--

| Robert George            |  Army Research Laboratory              |
| robertg@assb01.arl.mil   |  AMSRL-SS-IC                           |
| Voice: (408) 656-3316    |  2800 Powder Mill Road                 |
| Fax:   (408) 656-2814    |  Adelphi, MD 20783-1197                |  

For in much wisdom is much grief: and he that increaseth knowledge increaseth
sorrow.
    --Ecclesiastes 1:18